Stopwatch

A Simple Stopwatch implemented on an FPGA board using Verilog HDL.

Time elapsed counter testbench simulation

rst= 1 bit binary signal to reset count

clk = 1-bit binary signal to toggle count

ss = 6 bit register(stores upto 59D secs) to store the seconds elapsed.

mm = 6 bit register(stores upto 59D mins) to store the minutes elapsed.

Time elapsed counter Synthesized Schematic

Uses 40 Buffers and LUTs in total