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segment reboot every 45 seconds
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@jr1221
jr1221 committed Jan 25, 2025
1 parent 3426aaa commit 89db8b6
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Showing 5 changed files with 69 additions and 23 deletions.
7 changes: 7 additions & 0 deletions Core/Inc/adi_interaction.h
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Original file line number Diff line number Diff line change
Expand Up @@ -123,6 +123,13 @@ void set_discharge_timeout(cell_asic *chip, uint8_t timeout);

// --- BEGIN WRITE COMMANDS ---

/**
* @brief Soft reset all chips, then re-wake them
*
* @param chips
*/
void soft_reset_chips(cell_asic chips[NUM_CHIPS]);

/**
* @brief Write config registers. Wakes chips before writing.
*
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9 changes: 9 additions & 0 deletions Core/Inc/segment.h
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Original file line number Diff line number Diff line change
Expand Up @@ -46,6 +46,15 @@ void segment_configure_balancing(
*/
bool segment_is_balancing(cell_asic chips[NUM_CHIPS]);


/**
* @brief Reset, then wake, then re-configure all chips
*
* @param bmsdata
*/
void segment_restart(acc_data_t *bmsdata);


/**
* @brief Do a single shot, redundant C-ADC measurement and read
* the contents of Status Register Group C, which contains the
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49 changes: 33 additions & 16 deletions Core/Src/adi_interaction.c
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Original file line number Diff line number Diff line change
Expand Up @@ -107,7 +107,7 @@ void set_discharge_timeout(cell_asic *chip, uint8_t timeout)

// void start_cell_voltages_adc(cell_asic chips[NUM_CHIPS])
// {
// adbms_wake();
// adbms_wake_isospi();
// adBms6830_Adcv(RD_ON, CONTINUOUS, DCP_OFF, RSTF_OFF, OW_OFF_ALL_CH);
// adBmsPollAdc(PLCADC);
// }
Expand All @@ -133,10 +133,10 @@ inline void delay_us(uint16_t us)
}

/**
* @brief Wake every ADBMS6830 IC in the daisy chain. Blocking wait for around 30us * NUM_CHIPS.
* @brief Wake the isoSPI of every ADBMS6830 IC in the daisy chain. Blocking wait for around 30us * NUM_CHIPS.
*
*/
void adbms_wake()
void adbms_wake_isospi()
{
for (uint8_t ic = 0; ic < NUM_CHIPS; ic++) {
adBmsCsLow();
Expand All @@ -145,6 +145,18 @@ void adbms_wake()
}
}

/**
* @brief Wake the chip of every ADBMS6830 IC. Blocking wait about 1ms * NUM_CHIPS
*
*/
void adbms_wake_core() {
for (uint8_t ic = 0; ic < NUM_CHIPS; ic++) {
adBmsCsLow();
adBmsCsHigh();
delay_us(1000);
}
}

/**
* @brief Write data to all chips.
*
Expand All @@ -156,7 +168,7 @@ void adbms_wake()
void write_adbms_data(cell_asic chips[NUM_CHIPS], uint8_t command[2], TYPE type,
GRP group)
{
adbms_wake();
adbms_wake_isospi();

for (uint8_t chip = 0; chip < NUM_CHIPS; chip++) {
adBmsWriteData(NUM_CHIPS, &chips[chip], command, type, group);
Expand All @@ -174,7 +186,7 @@ void write_adbms_data(cell_asic chips[NUM_CHIPS], uint8_t command[2], TYPE type,
void read_adbms_data(cell_asic chips[NUM_CHIPS], uint8_t command[2], TYPE type,
GRP group)
{
adbms_wake();
adbms_wake_isospi();

for (uint8_t chip = 0; chip < NUM_CHIPS; chip++) {
adBmsReadData(NUM_CHIPS, &chips[chip], command, type, group);
Expand Down Expand Up @@ -216,6 +228,11 @@ void read_adbms_data(cell_asic chips[NUM_CHIPS], uint8_t command[2], TYPE type,

// --- BEGIN WRITE COMMANDS ---

void soft_reset_chips(cell_asic chips[NUM_CHIPS]) {
write_adbms_data(chips, SRST, Comm, NONE);
adbms_wake_core();
}

void write_config_regs(cell_asic chips[NUM_CHIPS])
{
write_adbms_data(chips, WRCFGA, Config, A);
Expand Down Expand Up @@ -257,7 +274,7 @@ void read_filtered_voltage_registers(cell_asic chips[NUM_CHIPS])
void adc_and_read_aux_registers(cell_asic chips[NUM_CHIPS])
{
// TODO only poll correct GPIOs
adbms_wake();
adbms_wake_isospi();
adBms6830_Adax(AUX_OW_OFF, PUP_DOWN, AUX_ALL);
adBmsPollAdc(PLAUX2);

Expand All @@ -269,7 +286,7 @@ void adc_and_read_aux_registers(cell_asic chips[NUM_CHIPS])

void adc_and_read_aux2_registers(cell_asic chips[NUM_CHIPS])
{
adbms_wake();
adbms_wake_isospi();
adBms6830_Adax2(AUX_ALL);
adBmsPollAdc(PLAUX2);

Expand Down Expand Up @@ -304,7 +321,7 @@ void read_serial_id(cell_asic chips[NUM_CHIPS])

void get_c_adc_voltages(cell_asic chips[NUM_CHIPS])
{
adbms_wake();
adbms_wake_isospi();
// Take single shot measurement
adBms6830_Adcv(RD_OFF, SINGLE, DCP_OFF, RSTF_OFF, OW_OFF_ALL_CH);
adBmsPollAdc(PLCADC);
Expand All @@ -314,11 +331,11 @@ void get_c_adc_voltages(cell_asic chips[NUM_CHIPS])
void get_s_adc_voltages(cell_asic chips[NUM_CHIPS])
{
write_config_regs(chips);
adbms_wake();
adbms_wake_isospi();
adBms6830_Adsv(SINGLE, DCP_OFF, OW_OFF_ALL_CH);
adBmsPollAdc(PLSADC);

adbms_wake();
adbms_wake_isospi();
read_adbms_data(chips, RDSALL, Rdsall, ALL_GRP);
// read_adbms_data(chip, RDSVA, S_volt, A);
// read_adbms_data(chip, RDSVB, S_volt, B);
Expand All @@ -330,33 +347,33 @@ void get_s_adc_voltages(cell_asic chips[NUM_CHIPS])

void get_avgd_cell_voltages(cell_asic chips[NUM_CHIPS])
{
adbms_wake();
adbms_wake_isospi();
adBms6830_Adcv(RD_ON, CONTINUOUS, DCP_OFF, RSTF_OFF, OW_OFF_ALL_CH);
adBmsPollAdc(PLCADC);

adbms_wake();
adbms_wake_isospi();
read_adbms_data(chips, RDACALL, Rdacall, ALL_GRP);
}

void get_filtered_cell_voltages(cell_asic chips[NUM_CHIPS])
{
adbms_wake();
adbms_wake_isospi();
read_adbms_data(chips, RDFCALL, Rdfcall, ALL_GRP);
}

void get_c_and_s_adc_voltages(cell_asic chips[NUM_CHIPS])
{
adbms_wake();
adbms_wake_isospi();
adBms6830_Adcv(RD_ON, CONTINUOUS, DCP_OFF, RSTF_OFF, OW_OFF_ALL_CH);
adBmsPollAdc(PLCADC);

adbms_wake();
adbms_wake_isospi();
read_adbms_data(chips, RDCSALL, Rdcsall, ALL_GRP);
}

void start_c_adc_conv()
{
adbms_wake();
adbms_wake_isospi();
adBms6830_Adcv(RD_ON, CONTINUOUS, DCP_OFF, RSTF_ON, OW_OFF_ALL_CH);
}

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9 changes: 8 additions & 1 deletion Core/Src/segment.c
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Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ void init_chip(cell_asic *chip)
{
set_REFON(chip, PWR_UP);
// WARNING, THE ENUM IS WRONG, CHECK TABLE 102
set_volt_adc_comp_thresh(chip, CVT_45mV);
set_volt_adc_comp_thresh(chip, CVT_135mV);
chip->tx_cfga.flag_d = 0;

// Short soak on ADAX
Expand Down Expand Up @@ -207,6 +207,13 @@ void segment_retrieve_debug_data(acc_data_t *bmsdata)

// read the above into status registers
read_status_registers(bmsdata->chips);

//segment_adc_comparison(bmsdata);
}

void segment_restart(acc_data_t *bmsdata) {
soft_reset_chips(bmsdata->chips);
segment_init(bmsdata);
}

bool segment_is_balancing(cell_asic chips[NUM_CHIPS])
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18 changes: 12 additions & 6 deletions Core/Src/shep_tasks.c
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Original file line number Diff line number Diff line change
Expand Up @@ -29,9 +29,21 @@ const osThreadAttr_t get_segment_data_attrs = { .name = "Get Segment Data",
void vGetSegmentData(void *pv_params)
{
acc_data_t *bmsdata = (acc_data_t *)pv_params;

int i = 0;
for (;;) {
// printf("Get segment data\n");
segment_retrieve_data(bmsdata);

if (DEBUG_MODE_ENABLED) {
segment_retrieve_debug_data(bmsdata);
}

if (++i % (45 * SAMPLE_RATE) == 0) {
printf(" *********** REBOOTING SEGMENT\n\n");
segment_restart(bmsdata);
}

osThreadFlagsSet(analyzer_thread, ANALYZER_FLAG);
osDelay(1000 / SAMPLE_RATE);
}
Expand Down Expand Up @@ -111,12 +123,6 @@ void vDebugMode(void *pv_params)
acc_data_t *bmsdata = (acc_data_t *)pv_params;

while (69 < 420) {
// get_adc_comparison(bmsdata);

// read_serial_id(bmsdata->chips);

segment_retrieve_debug_data(bmsdata);

for (int chip = 0; chip < NUM_CHIPS; chip++) {
uint8_t num_cells =
get_num_cells(&bmsdata->chip_data[chip]);
Expand Down

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