Support Full-Speed PRE packet handling #19
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RXCmdFilter test code was not updated alongside actual module, most likely due to changed Migen simulator. Create new unit test based on old test code.
Do not use ClockDomainsRenamer in ULPI ctrl class. Add all synchronous statements to ulpi clock domain explicitly and use ClockDomainsRenamer only for the FSM. No funcitonal changes, however the resulting verilog and thus bitstream is slightly different. The only difference in verilog is that signals previously named: * platform_clockdomainsrenamer_state * platform_clockdomainsrenamer_next_state are now respectively named: * platform_ulpi_ctrl_state * platform_ulpi_ctrl_next_state
Use per packet speed information while interpreting packets to show PRE or ERR based on captured speed.
Add option to automatically switch between Full-Speed and Low-Speed packet capture after Full-Speed preamble (PRE packet) is captured.
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Convert cfilt test code to unit test
RXCmdFilter test code was not updated alongside actual module, most likely due to changed Migen simulator. Create new unit test based on old test code.
Explicitly use ulpi clock in ULPI control module
Do not use ClockDomainsRenamer in ULPI ctrl class. Add all synchronous statements to ulpi clock domain explicitly and use ClockDomainsRenamer only for the FSM.
No funcitonal changes, however the resulting verilog and thus bitstream is slightly different. The only difference in verilog is that signals previously named:
are now respectively named:
Store transceiver speed in packet flags
Use per packet speed information while interpreting packets to show PRE or ERR based on captured speed.
Add option to automatically switch between Full-Speed and Low-Speed packet capture after Full-Speed preamble (PRE packet) is captured.
Fix: #15