Support Sscofpmf extension CSRs and IRQ

configs/riscv64-xs-ref_defconfig

@@ -17,11 +17,18 @@ CONFIG_CLINT_MMIO=0x38000000
 # CONFIG_MULTICORE_DIFF is not set
 CONFIG_RVB=y
 CONFIG_RVK=y
+CONFIG_RV_ZICOND=y
 CONFIG_RVV=y
 CONFIG_RV_DEBUG=y
 CONFIG_RVH=y
 # CONFIG_RV_SDEXT is not set
 # CONFIG_RV_SDTRIG is not set
+CONFIG_RV_ZICNTR=y
+# CONFIG_RV_CSR_TIME is not set
+CONFIG_RV_ZIHPM=y
+CONFIG_RV_CSR_MCOUNTINHIBIT=y
+CONFIG_RV_CSR_MCOUNTINHIBIT_CNTR=y
+CONFIG_RV_CSR_MCOUNTINHIBIT_HPM=y
 # CONFIG_RV_PMP_ENTRY_0 is not set
 CONFIG_RV_PMP_ENTRY_16=y
 # CONFIG_RV_PMP_ENTRY_64 is not set
@@ -31,6 +38,7 @@ CONFIG_RV_PMP_ACTIVE_NUM=16
 CONFIG_PMP_GRANULARITY=12
 CONFIG_RV_PMP_CHECK=y
 CONFIG_RV_SVINVAL=y
+CONFIG_RV_SSCOFPMF=y
 CONFIG_MISA_UNCHANGEABLE=y
 CONFIG_XTVEC_VECTORED_MODE=y
 # CONFIG_TVAL_EX_II is not set

src/isa/riscv64/Kconfig

@@ -201,6 +201,10 @@ config RV_MSTATUS_FS_WRITABLE
   bool "make mstatus.fs writable; required for software FPU emulation"
   default y
 
+config RV_SSCOFPMF
+  bool "(Beta)Enable Sscofpmf extension(Supervisor-level Count OverFlow and Privilege Mode Filtering)"
+  default n
+
 config MISA_UNCHANGEABLE
   bool "Make misa cannot be changed by CSR write instructions like XS"
   default y

src/isa/riscv64/local-include/csr.h

@@ -127,6 +127,14 @@
 /** Supervisor State Enable Registers **/
 #define CSRS_S_STATE_ENABLE(f)
 
+#ifdef CONFIG_RV_SSCOFPMF
+  #define CSRS_S_SCOFPMF(f) \
+    f(scountovf, 0xDA0)
+#else
+  #define CSRS_S_SCOFPMF(f)
+#endif // CONFIG_RV_SSCOFPMF
+
+
 /** Supervisor Custom 1 **/
 #ifdef CONFIG_RV_SVINVAL
   #define CSRS_S_XIANGSHAN_SRNCTL(f) \
@@ -150,6 +158,7 @@
   CSRS_S_PROTECTION_TRANSLATION(f) \
   CSRS_S_DEBUG_TRACE(f) \
   CSRS_S_STATE_ENABLE(f) \
+  CSRS_S_SCOFPMF(f) \
   CSRS_S_CUSTOM_1(f)
 
 
@@ -403,38 +412,38 @@ CSR_STRUCT_START(mhartid)
 CSR_STRUCT_END(mhartid)
 
 CSR_STRUCT_START(mstatus)
-  uint64_t uie : 1;
-  uint64_t sie : 1;
-  uint64_t pad0: 1;
-  uint64_t mie : 1;
-  uint64_t upie: 1;
-  uint64_t spie: 1;
-  uint64_t pad1: 1;
-  uint64_t mpie: 1;
-  uint64_t spp : 1;
-  uint64_t vs  : 2;
-  uint64_t mpp : 2;
-  uint64_t fs  : 2;
-  uint64_t xs  : 2;
-  uint64_t mprv: 1;
-  uint64_t sum : 1;
-  uint64_t mxr : 1;
-  uint64_t tvm : 1;
-  uint64_t tw  : 1;
-  uint64_t tsr : 1;
-  uint64_t pad3: 9;
-  uint64_t uxl : 2;
-  uint64_t sxl : 2;
-  uint64_t sbe : 1;
-  uint64_t mbe : 1;
+  uint64_t pad0: 1; // [0]
+  uint64_t sie : 1; // [1]
+  uint64_t pad1: 1; // [2]
+  uint64_t mie : 1; // [3]
+  uint64_t pad2: 1; // [4]
+  uint64_t spie: 1; // [5]
+  uint64_t ube : 1; // [6]
+  uint64_t mpie: 1; // [7]
+  uint64_t spp : 1; // [8]
+  uint64_t vs  : 2; // [10:9]
+  uint64_t mpp : 2; // [12:11]
+  uint64_t fs  : 2; // [14:13]
+  uint64_t xs  : 2; // [16:15]
+  uint64_t mprv: 1; // [17]
+  uint64_t sum : 1; // [18]
+  uint64_t mxr : 1; // [19]
+  uint64_t tvm : 1; // [20]
+  uint64_t tw  : 1; // [21]
+  uint64_t tsr : 1; // [22]
+  uint64_t pad3: 9; // [31:23]
+  uint64_t uxl : 2; // [33:32]
+  uint64_t sxl : 2; // [35:34]
+  uint64_t sbe : 1; // [36]
+  uint64_t mbe : 1; // [37]
 #ifdef CONFIG_RVH
-  uint64_t gva : 1;
-  uint64_t mpv : 1;
-  uint64_t pad4:23;
+  uint64_t gva : 1; // [38]
+  uint64_t mpv : 1; // [39]
+  uint64_t pad4:23; // [62:40]
 #else
-  uint64_t pad4:25;
+  uint64_t pad4:25; // [62:38]
 #endif
-  uint64_t sd  : 1;
+  uint64_t sd  : 1; // [63]
 CSR_STRUCT_END(mstatus)
 
 typedef enum ExtContextStatus {
@@ -687,6 +696,11 @@ CSR_STRUCT_START(satp)
   uint64_t mode: 4;
 CSR_STRUCT_END(satp)
 
+#ifdef CONFIG_RV_SSCOFPMF
+CSR_STRUCT_START(scountovf)
+CSR_STRUCT_END(scountovf)
+#endif
+
 /** Supervisor Custom CSRs **/
 
 #ifdef CONFIG_RV_SVINVAL

src/isa/riscv64/local-include/intr.h

@@ -29,7 +29,7 @@ enum {
   EX_SAM, // store/amo address misaligned
   EX_SAF, // store/amo address fault
   EX_ECU, // ecall from U-mode or VU-mode
-  EX_ECS, // ecall from HS-mode 
+  EX_ECS, // ecall from HS-mode
   EX_ECVS,// ecall from VS-mode, H-extention
   EX_ECM, // ecall from M-mode
   EX_IPF, // instruction page fault
@@ -42,6 +42,25 @@ enum {
   EX_SGPF // store/amo guest-page fault, H-extention
 };
 
+enum {
+  IRQ_USIP,  // reserved yet
+  IRQ_SSIP,
+  IRQ_VSSIP,
+  IRQ_MSIP,
+  IRQ_UTIP,  // reserved yet
+  IRQ_STIP,
+  IRQ_VSTIP,
+  IRQ_MTIP,
+  IRQ_UEIP,  // reserved yet
+  IRQ_SEIP,
+  IRQ_VSEIP,
+  IRQ_MEIP,
+  IRQ_SGEI,  // Supervisor guest external interrupt
+  IRQ_LCOFI, // Local counter overflow interrupt
+};
+
+#define INTR_BIT (1ULL << 63)
+
 // now NEMU does not support EX_IAM,
 // so it may ok to use EX_IAM to indicate a successful memory access
 #define MEM_OK 0

src/isa/riscv64/system/intr.c

@@ -21,12 +21,6 @@
 
 void update_mmu_state();
 
-#define INTR_BIT (1ULL << 63)
-enum {
-  IRQ_USIP, IRQ_SSIP, IRQ_VSSIP, IRQ_MSIP,
-  IRQ_UTIP, IRQ_STIP, IRQ_VSTIP, IRQ_MTIP,
-  IRQ_UEIP, IRQ_SEIP, IRQ_VSEIP, IRQ_MEIP, IRQ_SGEI
-};
 
 #ifdef CONFIG_RVH
 bool intr_deleg_S(word_t exceptionNO) {
@@ -62,6 +56,7 @@ static word_t get_trap_pc(word_t xtvec, word_t xcause) {
 }
 
 word_t raise_intr(word_t NO, vaddr_t epc) {
+  Logti("raise intr cause NO: %ld, epc: %lx\n", NO, epc);
 #ifdef CONFIG_DIFFTEST_REF_SPIKE
   switch (NO) {
 #ifdef CONFIG_RVH

src/isa/riscv64/system/priv.c

@@ -215,6 +215,9 @@ static inline word_t* csr_decode(uint32_t addr) {
 #define HIE_WMASK HS_MASK
 #endif
 
+#define MIDELEG_WMASK_BASE 0x222
+#define MIDELEG_WMASK MUXDEF(CONFIG_RV_SSCOFPMF, (MIDELEG_WMASK_BASE | 1 << IRQ_LCOFI), MIDELEG_WMASK_BASE)
+
 #define MIE_MASK_BASE 0xaaa
 #define MIP_MASK_BASE ((1 << 9) | (1 << 5) | (1 << 1))
 #ifdef CONFIG_RVH
@@ -234,6 +237,9 @@ static inline word_t* csr_decode(uint32_t addr) {
 #define FRM_MASK 0x07
 #define FCSR_MASK 0xff
 #define SATP_SV39_MASK 0xf000000000000000ULL
+
+#define SCOUNTOVF_WMASK 0xfffffff8ULL
+
 #define is_read(csr) (src == (void *)(csr))
 #define is_write(csr) (dest == (void *)(csr))
 #define mask_bitset(old, mask, new) (((old) & ~(mask)) | ((new) & (mask)))
@@ -530,7 +536,7 @@ static inline void csr_write(word_t *dest, word_t src) {
     }
     else if( is_write(stvec))  {vstvec->val = src & ~(0x2UL);}
   }else if (is_write(mideleg)){
-    *dest = (src & 0x222) | MIDELEG_FORCED_MASK;
+    *dest = (src & MIDELEG_WMASK) | MIDELEG_FORCED_MASK;
   }else if (is_write(hideleg)){
     hideleg->val = mask_bitset(hideleg->val, VS_MASK, src);
   }else if (is_write(hie)){
@@ -739,8 +745,9 @@ static inline void csr_write(word_t *dest, word_t src) {
     // Only support Sv39, ignore write that sets other mode
     if ((src & SATP_SV39_MASK) >> 60 == 8 || (src & SATP_SV39_MASK) >> 60 == 0)
       *dest = MASKED_SATP(src);
-#ifdef CONFIG_RV_SDTRIG
-  } else if (is_write(tselect)) {
+  }
+#ifdef CONFIG_RVSDTRIG
+  else if (is_write(tselect)) {
     *dest = src < CONFIG_TRIGGER_NUM ? src : CONFIG_TRIGGER_NUM;
   } else if (is_write(tdata1)) {
     // not write to dest
@@ -766,8 +773,11 @@ static inline void csr_write(word_t *dest, word_t src) {
     tdata2_t* tdata2_reg = &cpu.TM->triggers[tselect->val].tdata2;
     tdata2_t wdata = *(tdata2_t*)&src;
     tdata2_reg->val = wdata.val;
-#endif // CONFIG_RV_SDTRIG
   }
+#endif // CONFIG_RVSDTRIG
+#ifdef CONFIG_RV_SSCOFPMF
+  else if (is_write(scountovf)) { *dest = src & SCOUNTOVF_WMASK; }
+#endif // CONFIG_RV_SSCOFPMF
 #ifdef CONFIG_RVH
   else if (is_write(hgatp)) {
     hgatp_t new_val = (hgatp_t)src;