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submodule(coupledL2): bump coupledL2
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Ma-YX committed Nov 20, 2024
1 parent db9738a commit 27e0ab2
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Showing 2 changed files with 6 additions and 2 deletions.
6 changes: 5 additions & 1 deletion src/main/scala/xiangshan/L2Top.scala
Original file line number Diff line number Diff line change
Expand Up @@ -173,7 +173,8 @@ class L2TopInlined()(implicit p: Parameters) extends LazyModule

val resetDelayN = Module(new DelayN(UInt(PAddrBits.W), 5))

beu.module.io.errors <> io.beu_errors
beu.module.io.errors.icache := io.beu_errors.icache
beu.module.io.errors.dcache := io.beu_errors.dcache
resetDelayN.io.in := io.reset_vector.fromTile
io.reset_vector.toCore := resetDelayN.io.out
io.hartId.toCore := io.hartId.fromTile
Expand Down Expand Up @@ -234,6 +235,9 @@ class L2TopInlined()(implicit p: Parameters) extends LazyModule
io.chi.get <> l2.io_chi
case l2cache: TL2TLCoupledL2 =>
}

beu.module.io.errors.l2.ecc_error.valid := l2.io.error.valid
beu.module.io.errors.l2.ecc_error.bits := l2.io.error.address
} else {
io.l2_hint := 0.U.asTypeOf(io.l2_hint)
io.debugTopDown <> DontCare
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