fix(trace): remove traceTrap & tracePriv from trace pipeline

src/main/scala/xiangshan/Parameters.scala

@@ -545,8 +545,6 @@ case class XSCoreParameters
   // Parameters for trace extension.
   // Trace parameters is useful for XSTOP.
   val traceParams: TraceParams = new TraceParams(
-    HasEncoder     = true,
-    TraceEnable    = true,
     TraceGroupNum  = 3,
     IaddrWidth     = GPAddrBitsSv48x4,
     PrivWidth      = 3,
@@ -895,8 +893,6 @@ trait HasXSParameter {
 
   // Parameters for Trace extension
   def TraceGroupNum          = coreParams.traceParams.TraceGroupNum
-  def HasEncoder             = coreParams.traceParams.HasEncoder
-  def TraceEnable            = coreParams.traceParams.TraceEnable
   def CauseWidth             = XLEN
   def TvalWidth              = coreParams.traceParams.IaddrWidth
   def PrivWidth              = coreParams.traceParams.PrivWidth

src/main/scala/xiangshan/backend/Backend.scala

@@ -247,6 +247,7 @@ class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parame
   ctrlBlock.io.fromTop.hartId := io.fromTop.hartId
   ctrlBlock.io.frontend <> io.frontend
   ctrlBlock.io.fromCSR.toDecode := intExuBlock.io.csrToDecode.get
+  ctrlBlock.io.fromCSR.traceCSR := intExuBlock.io.csrio.get.traceCSR
   ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback
   ctrlBlock.io.fromMem.stIn <> io.mem.stIn
   ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation
@@ -256,8 +257,6 @@ class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parame
   ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt
   ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget
   ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet
-  ctrlBlock.io.robio.csr.traceTrapInfo := intExuBlock.io.csrio.get.traceTrapInfo
-  ctrlBlock.io.robio.csr.tracePriv := intExuBlock.io.csrio.get.tracePriv
   ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event
   ctrlBlock.io.robio.csr.criticalErrorState := intExuBlock.io.csrio.get.criticalErrorState
   ctrlBlock.io.robio.lsq <> io.mem.robLsqIO

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -245,38 +245,30 @@ class CtrlBlockImp(
    * trace begin
    */
   val trace = Module(new Trace)
-  if(HasEncoder){
-    trace.io.fromEncoder.stall  := io.traceCoreInterface.fromEncoder.stall
-    trace.io.fromEncoder.enable := io.traceCoreInterface.fromEncoder.enable
-  } else if(!HasEncoder && TraceEnable) {
-    trace.io.fromEncoder.enable := true.B
-    trace.io.fromEncoder.stall  := false.B
-  } else if(!HasEncoder && !TraceEnable) {
-    trace.io.fromEncoder.enable := false.B
-    trace.io.fromEncoder.stall  := false.B
-  }
-
-  trace.io.fromRob         := rob.io.trace.traceCommitInfo
-  rob.io.trace.blockCommit := trace.io.blockRobCommit
-
-  if(backendParams.debugEn){
-    dontTouch(trace.io.toEncoder)
-  }
-
+  trace.io.in.fromEncoder.stall  := io.traceCoreInterface.fromEncoder.stall
+  trace.io.in.fromEncoder.enable := io.traceCoreInterface.fromEncoder.enable
+  trace.io.in.fromRob            := rob.io.trace.traceCommitInfo
+  rob.io.trace.blockCommit       := trace.io.out.blockRobCommit
+
   for ((pcMemIdx, i) <- pcMemRdIndexes("trace").zipWithIndex) {
-    val traceValid = trace.toPcMem(i).valid
+    val traceValid = trace.toPcMem.blocks(i).valid
     pcMem.io.ren.get(pcMemIdx) := traceValid
-    pcMem.io.raddr(pcMemIdx) := trace.toPcMem(i).bits.ftqIdx.get.value
-    trace.io.fromPcMem(i) := pcMem.io.rdata(pcMemIdx).getPc(RegEnable(trace.toPcMem(i).bits.ftqOffset.get, traceValid))
+    pcMem.io.raddr(pcMemIdx) := trace.toPcMem.blocks(i).bits.ftqIdx.get.value
+    trace.io.in.fromPcMem(i) := pcMem.io.rdata(pcMemIdx).getPc(RegEnable(trace.toPcMem.blocks(i).bits.ftqOffset.get, traceValid))
   }
 
-  io.traceCoreInterface.toEncoder.cause     := trace.io.toEncoder.trap.cause.asUInt
-  io.traceCoreInterface.toEncoder.tval      := trace.io.toEncoder.trap.tval.asUInt
-  io.traceCoreInterface.toEncoder.priv      := trace.io.toEncoder.priv.asUInt
-  io.traceCoreInterface.toEncoder.iaddr     := VecInit(trace.io.toEncoder.blocks.map(_.bits.iaddr.get)).asUInt
-  io.traceCoreInterface.toEncoder.itype     := VecInit(trace.io.toEncoder.blocks.map(_.bits.tracePipe.itype)).asUInt
-  io.traceCoreInterface.toEncoder.iretire   := VecInit(trace.io.toEncoder.blocks.map(_.bits.tracePipe.iretire)).asUInt
-  io.traceCoreInterface.toEncoder.ilastsize := VecInit(trace.io.toEncoder.blocks.map(_.bits.tracePipe.ilastsize)).asUInt
+  // Trap/Xret only occor in block(0).
+  val tracePriv = Mux(Itype.isTrapOrXret(trace.toEncoder.blocks(0).bits.tracePipe.itype),
+    io.fromCSR.traceCSR.lastPriv,
+    io.fromCSR.traceCSR.currentPriv
+  )
+  io.traceCoreInterface.toEncoder.cause     := io.fromCSR.traceCSR.cause.asUInt
+  io.traceCoreInterface.toEncoder.tval      := io.fromCSR.traceCSR.tval.asUInt
+  io.traceCoreInterface.toEncoder.priv      := tracePriv
+  io.traceCoreInterface.toEncoder.iaddr     := VecInit(trace.io.out.toEncoder.blocks.map(_.bits.iaddr.get)).asUInt
+  io.traceCoreInterface.toEncoder.itype     := VecInit(trace.io.out.toEncoder.blocks.map(_.bits.tracePipe.itype)).asUInt
+  io.traceCoreInterface.toEncoder.iretire   := VecInit(trace.io.out.toEncoder.blocks.map(_.bits.tracePipe.iretire)).asUInt
+  io.traceCoreInterface.toEncoder.ilastsize := VecInit(trace.io.out.toEncoder.blocks.map(_.bits.tracePipe.ilastsize)).asUInt
 
   /**
    * trace end
@@ -730,6 +722,7 @@ class CtrlBlockIO()(implicit p: Parameters, params: BackendParams) extends XSBun
   val frontend = Flipped(new FrontendToCtrlIO())
   val fromCSR = new Bundle{
     val toDecode = Input(new CSRToDecode)
+    val traceCSR = Input(new TraceCSR)
   }
   val toIssueBlock = new Bundle {
     val flush = ValidIO(new Redirect)

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -100,8 +100,8 @@ class CSRFileIO(implicit p: Parameters) extends XSBundle {
   val trapTarget = Output(new TargetPCBundle)
   val interrupt = Output(Bool())
   val wfi_event = Output(Bool())
-  val traceTrapInfo = ValidIO(new TraceTrap)
-  val tracePriv = Output(new TracePriv)
+  //trace
+  val traceCSR = Output(new TraceCSR)
   // from LSQ
   val memExceptionVAddr = Input(UInt(XLEN.W))
   val memExceptionGPAddr = Input(UInt(XLEN.W))

src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala

@@ -190,8 +190,7 @@ class NewCSR(implicit val p: Parameters) extends Module
       // Instruction fetch address translation type
       val instrAddrTransType = new AddrTransType
       // trace
-      val traceTrapInfo = ValidIO(new TraceTrap)
-      val tracePriv = Output(new TracePriv)
+      val traceCSR = Output(new TraceCSR)
       // custom
       val custom = new CSRCustomState
       val criticalErrorState = Bool()
@@ -1124,14 +1123,13 @@ class NewCSR(implicit val p: Parameters) extends Module
   val currentPriv = privForTrace
   val lastPriv = RegEnable(privForTrace, Priv.M, (xret || io.fromRob.trap.valid))
 
-  io.status.tracePriv.lastPriv       := lastPriv
-  io.status.tracePriv.currentPriv    := privForTrace
-  io.status.traceTrapInfo.valid      := RegNext(io.fromRob.trap.valid)
-  io.status.traceTrapInfo.bits.cause := Mux1H(
+  io.status.traceCSR.lastPriv       := lastPriv
+  io.status.traceCSR.currentPriv    := privForTrace
+  io.status.traceCSR.cause := Mux1H(
     Seq(privState.isModeM, privState.isModeHS, privState.isModeVS),
     Seq(mcause.rdata,      scause.rdata,       vscause.rdata)
   )
-  io.status.traceTrapInfo.bits.tval  := Mux1H(
+  io.status.traceCSR.tval  := Mux1H(
     Seq(privState.isModeM, privState.isModeHS, privState.isModeVS),
     Seq(mtval.rdata,       stval.rdata,        vstval.rdata)
   )

src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala

@@ -309,8 +309,7 @@ class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg)
 
   csrOut.debugMode := csrMod.io.status.debugMode
 
-  csrOut.traceTrapInfo := csrMod.io.status.traceTrapInfo
-  csrOut.tracePriv     := csrMod.io.status.tracePriv
+  csrOut.traceCSR := csrMod.io.status.traceCSR
 
   csrOut.customCtrl match {
     case custom =>

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -459,7 +459,6 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
         lastIsRVC := io.in(j).bits.preDecodeInfo.isRVC
       }
     }
-
     uops(i).traceBlockInPipe.ilastsize := Mux(canRobCompressVec(i),
       Mux(lastIsRVC, Ilastsize.HalfWord, Ilastsize.Word),
       (if(i < RenameWidth -1) Mux(isFusionVec(i), iLastSizeVec(i+1), iLastSizeVec(i)) else iLastSizeVec(i))

src/main/scala/xiangshan/backend/rob/Rob.scala

@@ -1231,12 +1231,8 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
   /**
    * trace
    */
-  val traceTrapInfoFromCsr = io.csr.traceTrapInfo
-  val tracePrivInfoFromCsr = io.csr.tracePriv
 
   // trace output
-  val traceTrap = io.trace.traceCommitInfo.trap
-  val tracePriv = io.trace.traceCommitInfo.priv
   val traceValids = io.trace.traceCommitInfo.blocks.map(_.valid)
   val traceBlocks = io.trace.traceCommitInfo.blocks
   val traceBlockInPipe = io.trace.traceCommitInfo.blocks.map(_.bits.tracePipe)
@@ -1245,38 +1241,22 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
     traceBlocks(i).bits.ftqIdx.foreach(_ := rawInfo(i).ftqIdx)
     traceBlocks(i).bits.ftqOffset.foreach(_ := rawInfo(i).ftqOffset)
     traceBlockInPipe(i).itype := rawInfo(i).traceBlockInPipe.itype
-    traceBlockInPipe(i).iretire := Mux(io.commits.isCommit && io.commits.commitValid(i), rawInfo(i).traceBlockInPipe.iretire, 0.U)
+    traceBlockInPipe(i).iretire := rawInfo(i).traceBlockInPipe.iretire
     traceBlockInPipe(i).ilastsize := rawInfo(i).traceBlockInPipe.ilastsize
-  }
-
-  for (i <- 0 until CommitWidth) {
-    val iretire = traceBlocks(i).bits.tracePipe.iretire
-    val itype   = traceBlocks(i).bits.tracePipe.itype
-    traceValids(i) := iretire =/= 0.U
-  }
-
-  val t_idle :: t_waiting :: Nil = Enum(2)
-  val traceState = RegInit(t_idle)
-  when(traceState === t_idle){
-    when(io.exception.valid){
-      traceState := t_waiting
-    }
-  }.elsewhen(traceState === t_waiting){
-    when(traceTrapInfoFromCsr.valid){
-      traceState := t_idle
-      traceBlocks(0).bits.tracePipe.itype := Mux(io.exception.bits.isInterrupt,
-        Itype.Interrupt,
-        Itype.Exception
-      )
-      traceValids(0) := true.B
+    traceValids(i) := io.commits.isCommit && io.commits.commitValid(i)
+    // exception only occor block(0).
+    if(i == 0) {
+      when(io.exception.valid){
+        traceBlocks(i).bits.tracePipe.itype := Mux(io.exception.bits.isInterrupt,
+          Itype.Interrupt,
+          Itype.Exception
+        )
+        traceValids(i) := true.B
+        traceBlockInPipe(i).iretire := 0.U
+      }
     }
   }
-  traceTrap := traceTrapInfoFromCsr.bits
-  tracePriv := Mux(traceValids(0) && Itype.isTrapOrXret(traceBlocks(0).bits.tracePipe.itype),
-    tracePrivInfoFromCsr.lastPriv,
-    tracePrivInfoFromCsr.currentPriv
-  )
-
+
   /**
    * debug info
    */

src/main/scala/xiangshan/backend/rob/RobBundles.scala

@@ -217,8 +217,6 @@ class RobCSRIO(implicit p: Parameters) extends XSBundle {
   val isXRet     = Input(Bool())
   val wfiEvent   = Input(Bool())
   val criticalErrorState = Input(Bool())
-  val traceTrapInfo = Flipped(ValidIO(new TraceTrap))
-  val tracePriv = Input(new TracePriv)
 
   val fflags     = Output(Valid(UInt(5.W)))
   val vxsat      = Output(Valid(Bool()))

src/main/scala/xiangshan/backend/trace/Interface.scala

@@ -7,12 +7,9 @@ import utils.NamedUInt
 import xiangshan.HasXSParameter
 import xiangshan.frontend.{BrType, FtqPtr, PreDecodeInfo}
 
-class TraceTrap(implicit val p: Parameters) extends Bundle with HasXSParameter {
+class TraceCSR(implicit val p: Parameters) extends Bundle with HasXSParameter {
   val cause = UInt(CauseWidth.W)
   val tval  = UInt(TvalWidth.W)
-}
-
-class TracePriv extends Bundle  {
   val lastPriv    = Priv()
   val currentPriv = Priv()
 }
@@ -31,8 +28,6 @@ class TraceBlock(hasIaddr: Boolean, iretireWidth: Int)(implicit val p: Parameter
 }
 
 class TraceBundle(hasIaddr: Boolean, blockSize: Int, iretireWidth: Int)(implicit val p: Parameters) extends Bundle with HasXSParameter {
-  val priv = Priv()
-  val trap = Output(new TraceTrap)
   val blocks = Vec(blockSize, ValidIO(new TraceBlock(hasIaddr, iretireWidth)))
 }
 

src/main/scala/xiangshan/backend/trace/Trace.scala

@@ -6,8 +6,6 @@ import org.chipsalliance.cde.config.Parameters
 import xiangshan.HasXSParameter
 
 class TraceParams(
-  val HasEncoder     : Boolean,
-  val TraceEnable    : Boolean,
   val TraceGroupNum  : Int,
   val IaddrWidth     : Int,
   val PrivWidth      : Int,
@@ -16,37 +14,34 @@ class TraceParams(
 )
 
 class TraceIO(implicit val p: Parameters) extends Bundle with HasXSParameter {
-  val fromEncoder    = Input(new FromEncoder)
-  val fromRob        = Flipped(new TraceBundle(hasIaddr = false, CommitWidth, IretireWidthInPipe))
-  val blockRobCommit = Output(Bool())
-  val toPcMem        = Vec(TraceGroupNum, ValidIO(new TraceBlock(false, IretireWidthCompressed)))
-  val fromPcMem      = Input(Vec(TraceGroupNum, UInt(IaddrWidth.W)))
-  val toEncoder      = new TraceBundle(hasIaddr = true, TraceGroupNum, IretireWidthCompressed)
+  val in = new Bundle {
+    val fromEncoder    = Input(new FromEncoder)
+    val fromRob        = Flipped(new TraceBundle(hasIaddr = false, CommitWidth, IretireWidthInPipe))
+    val fromPcMem      = Input(Vec(TraceGroupNum, UInt(IaddrWidth.W)))
+  }
+  val out = new Bundle {
+    val toPcMem        = new TraceBundle(hasIaddr = false, TraceGroupNum, IretireWidthCompressed)
+    val toEncoder      = new TraceBundle(hasIaddr = true,  TraceGroupNum, IretireWidthCompressed)
+    val blockRobCommit = Output(Bool())
+  }
 }
 
 class Trace(implicit val p: Parameters) extends Module with HasXSParameter {
   val io = IO(new TraceIO)
-  val (fromEncoder, fromRob, toPcMem, fromPcMem, toEncoder) = (io.fromEncoder, io.fromRob, io.toPcMem, io.fromPcMem, io.toEncoder)
+  val (fromEncoder, fromRob, fromPcMem, toPcMem, toEncoder) = (io.in.fromEncoder, io.in.fromRob, io.in.fromPcMem, io.out.toPcMem, io.out.toEncoder)
 
   /**
    * stage 0: CommitInfo from rob
    */
   val blockCommit = Wire(Bool())
-  io.blockRobCommit := blockCommit
+  io.out.blockRobCommit := blockCommit
 
   /**
    * stage 1: regNext(robCommitInfo)
    */
   val s1_in = fromRob
   val s1_out = WireInit(0.U.asTypeOf(s1_in))
-
   for(i <- 0 until CommitWidth) {
-    // Trap/Xret only occor in block(0).
-    if(i == 0) {
-      s1_out.priv := RegEnable(s1_in.priv, s1_in.blocks(0).valid)
-      s1_out.trap.cause := RegEnable(s1_in.trap.cause, 0.U, s1_in.blocks(0).valid && Itype.isTrap(s1_in.blocks(0).bits.tracePipe.itype))
-      s1_out.trap.tval := RegEnable(s1_in.trap.tval, 0.U, s1_in.blocks(0).valid && Itype.isTrap(s1_in.blocks(0).bits.tracePipe.itype))
-    }
     s1_out.blocks(i).valid := RegEnable(s1_in.blocks(i).valid, false.B, !blockCommit)
     s1_out.blocks(i).bits := RegEnable(s1_in.blocks(i).bits, 0.U.asTypeOf(s1_in.blocks(i).bits), s1_in.blocks(i).valid)
   }
@@ -66,23 +61,14 @@ class Trace(implicit val p: Parameters) extends Module with HasXSParameter {
    */
   val s3_in_groups = s2_out_groups
   val s3_out_groups = RegNext(s3_in_groups)
-
-  toPcMem := s3_in_groups.blocks
+  toPcMem := s3_in_groups
 
   for(i <- 0 until TraceGroupNum) {
-    toEncoder.priv := s3_out_groups.priv
-    toEncoder.trap := s3_out_groups.trap
     toEncoder.blocks(i).valid := s3_out_groups.blocks(i).valid
     toEncoder.blocks(i).bits.iaddr.foreach(_ := Mux(s3_out_groups.blocks(i).valid, fromPcMem(i), 0.U))
     toEncoder.blocks(i).bits.tracePipe := s3_out_groups.blocks(i).bits.tracePipe
   }
-  if(backendParams.debugEn){
-    dontTouch(io.toEncoder)
+  if(backendParams.debugEn) {
+    dontTouch(io.out.toEncoder)
   }
-}
-
-
-
-
-
-
+}