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area(ftq): use Vec(Reg) instead of template #3595

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in previous code, SyncDataModuleTemplate is used, which uses negedge register (1.5 + 1.5 cycle write + read) with bypass to achieve the same behaviour as simple rdata := reg(RegNext(raddr))

this commits removes the template since we are not using negedge registers anymore. All the bypass logic used in 1.5 + 1.5 can be eliminated. Also, on some FTQ queue that does not require immediate read result, no bypass is need. The commit also removes there bypasses.

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[Generated by IPC robot]
commit: 9ff8575

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
9ff8575 1.865 0.450 2.695 1.186 2.832 2.488 2.400 0.919 1.397 1.454 3.415 2.747 2.423 3.212

master branch:

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
6a8b2d5 1.855 0.450 2.695 1.186 2.832 2.488 2.400 0.919 1.397 1.454 3.415 2.747 2.423 3.212
a1d4641 1.855 0.450 2.695 1.186 2.832 2.488 2.400 0.919 1.397 1.454 3.415 2.747 2.423 3.212
110fa54 1.855 0.450 2.695 1.186 2.832 2.488 2.400 0.919 1.397 1.454 3.415 2.747 2.423 3.212
43f0874 1.865 0.450 2.695 1.186 2.832 2.488 2.400 0.919 1.397 1.454 3.415 2.747 2.423 3.212
b528775 1.865 0.450 2.695 1.186 2.832 2.488 2.400 0.919 1.397 1.454 3.415 2.747 2.423 3.212
c945b57 1.865 0.450 2.695 1.186 2.832 2.488 2.400 0.919 1.397 1.454 3.415 2.747 2.423 3.212
2ea10b4 1.855 0.450 2.695 1.186 2.832 2.488 2.400 0.919 1.397 1.454 3.415 2.747 2.423 3.212
90d824c 1.855 0.450 2.695 1.186 2.832 2.488 2.400 0.919 1.397 1.454 3.415 2.747 2.423 3.212
7e1c607 1.855 0.450 2.695 1.186 2.832 2.488 2.400 0.919 1.397 1.454 3.415 2.747 2.423 3.212

@eastonman eastonman force-pushed the area-remove-negedge-reg branch from 9ff8575 to 9088dcb Compare September 18, 2024 02:20
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[Generated by IPC robot]
commit: 9088dcb

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
9088dcb 1.934 0.450 2.695 1.194 2.812 2.465 2.400 0.916 1.397 1.626 3.426 2.747 2.429 3.271

master branch:

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
b4d41c1 1.858 0.450 2.695 1.186 2.801 2.445 2.400 0.919 1.397 1.433 3.393 2.747 2.423 3.212
52fc0c9 0.450 2.695 2.400 1.397 2.747
b7dc2d1 1.855 0.450 2.695 1.186 2.832 2.488 2.400 0.919 1.397 1.454 3.415 2.747 2.423 3.212
6a8b2d5 1.855 0.450 2.695 1.186 2.832 2.488 2.400 0.919 1.397 1.454 3.415 2.747 2.423 3.212
a1d4641 1.855 0.450 2.695 1.186 2.832 2.488 2.400 0.919 1.397 1.454 3.415 2.747 2.423 3.212
110fa54 1.855 0.450 2.695 1.186 2.832 2.488 2.400 0.919 1.397 1.454 3.415 2.747 2.423 3.212
43f0874 1.865 0.450 2.695 1.186 2.832 2.488 2.400 0.919 1.397 1.454 3.415 2.747 2.423 3.212
b528775 1.865 0.450 2.695 1.186 2.832 2.488 2.400 0.919 1.397 1.454 3.415 2.747 2.423 3.212
c945b57 1.865 0.450 2.695 1.186 2.832 2.488 2.400 0.919 1.397 1.454 3.415 2.747 2.423 3.212
2ea10b4 1.855 0.450 2.695 1.186 2.832 2.488 2.400 0.919 1.397 1.454 3.415 2.747 2.423 3.212

@eastonman eastonman force-pushed the area-remove-negedge-reg branch from 9088dcb to 230cf4e Compare September 19, 2024 14:49
in previous code, SyncDataModuleTemplate is used, which uses
negedge register (1.5 + 1.5 cycle write + read) with bypass to
achieve the same behaviour as simple rdata := reg(RegNext(raddr))

this commits removes the template since we are not using negedge
registers anymore. All the bypass logic used in 1.5 + 1.5 can be
eliminated. Also, on some FTQ queue that does not require
immediate read result, no bypass is need. The commit also removes
there bypasses.
@XiangShanRobot
Copy link

[Generated by IPC robot]
commit: 230cf4e

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
230cf4e 1.934 0.450 2.695 1.192 2.812 2.465 2.399 0.918 1.397 1.609 3.424 2.761 2.429 3.275

master branch:

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
7ff4ebd 1.934 0.450 2.695 1.192 2.812 2.465 2.399 0.918 1.397 1.609 3.424 2.761 2.429 3.275
db6cfb5 1.934 0.450 2.695 1.192 2.812 2.465 2.399 0.918 1.397 1.609 3.424 2.761 2.429 3.275
9d9b0bf 1.934 0.450 2.695 1.192 2.812 2.465 2.399 0.918 1.397 1.609 3.424 2.761 2.429 3.275
aef2231 1.934 0.450 2.695 1.192 2.812 2.465 2.399 0.918 1.397 1.609 3.424 2.761 2.429 3.275
20156f7 0.450 2.695 2.399 1.397 2.761
c0a99c0 1.934 0.450 2.695 1.192 2.812 2.465 2.399 0.918 1.397 1.609 3.424 2.761 2.429 3.275
b9db2c7 0.450 2.695 2.399 1.397 2.761
f3640a5 1.934 0.450 2.695 1.192 2.812 2.463 2.399 0.918 1.397 1.609 3.424 2.761 2.429 3.275
e0c1f27 0.450 2.695 2.399 1.397 2.761
8338e67 1.934 0.450 2.695 1.194 2.812 2.465 2.400 0.916 1.397 1.626 3.426 2.747 2.429 3.271

@eastonman eastonman added the do not merge Do not merge this pull request label Sep 20, 2024
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