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fix(aes): fix exception check for aes64ks1i. #3845

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Nov 25, 2024
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7 changes: 6 additions & 1 deletion src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
Original file line number Diff line number Diff line change
Expand Up @@ -864,6 +864,10 @@ class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstan
private val isCboInval = CBO_INVAL === io.enq.ctrlFlow.instr
private val isCboZero = CBO_ZERO === io.enq.ctrlFlow.instr

// Note that rnum of aes64ks1i must be in the range 0x0..0xA. The values 0xB..0xF are reserved.
private val isAes64ks1iIllegal =
FuType.FuTypeOrR(decodedInst.fuType, FuType.bku) && (decodedInst.fuOpType === BKUOpType.aes64ks1i) && inst.isRnumIllegal

private val exceptionII =
decodedInst.selImm === SelImm.INVALID_INSTR ||
vecException.io.illegalInst ||
Expand All @@ -885,7 +889,8 @@ class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstan
(decodedInst.needFrm.vectorNeedFrm || FuType.isVectorNeedFrm(decodedInst.fuType)) && io.fromCSR.illegalInst.frm ||
io.fromCSR.illegalInst.cboZ && isCboZero ||
io.fromCSR.illegalInst.cboCF && (isCboClean || isCboFlush) ||
io.fromCSR.illegalInst.cboI && isCboInval
io.fromCSR.illegalInst.cboI && isCboInval ||
isAes64ks1iIllegal

private val exceptionVI =
io.fromCSR.virtualInst.sfenceVMA && FuType.FuTypeOrR(decodedInst.fuType, FuType.fence) && decodedInst.fuOpType === FenceOpType.sfence ||
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -117,12 +117,21 @@ trait BitFieldsVec { this: Riscv32BitInst =>
}
}

trait BitFieldsRVK { this: Riscv32BitInst =>
def RNUM : UInt = inst(23, 20)

def isRnumIllegal = {
this.RNUM > 0xA.U
}
}

class XSInstBitFields extends Riscv32BitInst
with BitFieldsI
with BitFieldsS
with BitFieldsCSR
with BitFieldsFp
with BitFieldsVec
with BitFieldsRVK

class InstVType extends Bundle {
val reserved = UInt(3.W)
Expand Down
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