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rock 4se: add 6.86 inch display
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@Radxa-Alvin
Radxa-Alvin committed Apr 25, 2024
1 parent 31042d0 commit 1e1e197
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1 change: 1 addition & 0 deletions arch/arm64/boot/dts/rockchip/overlays/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -101,6 +101,7 @@ dtb-$(CONFIG_CPU_RK3399) += \
rock-4c-plus-radxa-display-8hd.dtbo \
rock-4c-plus-radxa-display-10fhd.dtbo \
rock-4c-plus-radxa-display-10hd.dtbo \
rock-4se-6_86inch-display.dtbo \
rock-4se-radxa-display-8hd.dtbo \
rock-4-radxa-display-10hd.dtbo

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238 changes: 238 additions & 0 deletions arch/arm64/boot/dts/rockchip/overlays/rock-4se-6_86inch-display.dts
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@@ -0,0 +1,238 @@
/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/display/drm_mipi_dsi.h>

/ {
metadata {
title = "ROCK 4SE 6.86inch Display";
compatible = "unknown";
category = "display";
exclusive = "dsi";
description = "ROCK 4SE 6.86inch Display";
};
};

&{/} {
backlight: backlight {
status = "okay";
compatible = "pwm-backlight";
pwms = <&pwm1 0 25000 0>;
brightness-levels = <
255 254 253 252 251 250 249 248
247 246 245 244 243 242 241 240
239 238 237 236 235 234 233 232
231 230 229 228 227 226 225 224
223 222 221 220 219 218 217 216
215 214 213 212 211 210 209 208
207 206 205 204 203 202 201 200
199 198 197 196 195 194 193 192
191 190 189 188 187 186 185 184
183 182 181 180 179 178 177 176
175 174 173 172 171 170 169 168
167 166 165 164 163 162 161 160
159 158 157 156 155 154 153 152
151 150 149 148 147 146 145 144
143 142 141 140 139 138 137 136
135 134 133 132 131 130 129 128
127 126 125 124 123 122 121 120
119 118 117 116 115 114 113 112
111 110 109 108 107 106 105 104
103 102 101 100 99 98 97 96
95 94 93 92 91 90 89 88
87 86 85 84 83 82 81 80
79 78 77 76 75 74 73 72
71 70 69 68 67 66 65 64
63 62 61 60 59 58 57 56
55 54 53 52 51 50 49 48
47 46 45 44 43 42 41 40
39 38 38 37 37 36 36 35
35 34 34 33 33 32 32 31
31 30 30 29 29 28 28 27
27 26 26 25 25 24 24 23
23 22 22 21 21 20 20 0
>;
default-brightness-level = <200>;
enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_backlight_en>;
};
};

&pwm1 {
status = "okay";
};

&dsi {
status = "okay";
dsi1-only;
};

&dsi1 {
status = "okay";
rockchip,dsi-dsi0 = <&dsi>;
#address-cells = <1>;
#size-cells = <0>;

dsi1_panel: panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;

backlight = <&backlight>;
power-supply = <&vcc3v3_sys>;
vdd-supply = <&vcc3v3_sys>;
vccio-supply = <&vcc_1v8>;

reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_panel_reset>;
dsi,lanes = <4>;
panel-init-sequence = [
15 00 04 B9 FF 83 94
15 00 07 BA 63 03 68 6B B2 C0
15 00 0B B1 48 14 74 09 32 54 71 51 57 3A
15 00 0D B2 00 A0 64 0D 0D 2E 11 40 00 00 C0 18
15 00 16 B4 02 76 02 76 02 76 05 05 88 55 00 1F 73 74 73 74 73 74 05 10 86
15 00 03 B6 20 20
15 00 2C D3 00 00 07 07 40 07 08 08 32 10 08 00 08 32 39 0C 05 0C 02 39 06 05 06 37 33 0B 0B 27 10 07 07 00 00 00 00 17 00 00 00 00 00 00 17
15 00 2D D5 27 26 25 24 07 06 05 04 03 02 01 00 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 21 20 23 22 18 18 18 18
15 00 2D D6 20 21 22 23 00 01 02 03 04 05 06 07 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 26 27 24 25 18 18 18 18
15 00 3B E0 00 03 0E 16 18 1D 21 1F 43 58 69 69 73 87 8D 92 9F A2 9F AD BB 5C 5A 5E 62 64 6A 79 7F 00 03 0E 16 18 1D 21 1F 43 58 69 69 73 87 8D 92 9F A2 9F AD BB 5C 5A 5E 62 64 6A 79 7F
15 00 02 CC 0B
15 00 03 C0 1F 31
15 00 02 D2 88
15 00 02 D4 02
15 00 02 BD 02
15 00 0D D8 FF FF FF FF FF F0 FF FF FF FF FF F0
15 00 02 BD 00
15 00 02 C6 FD
05 78 01 11
05 14 01 29
];

panel-exit-sequence = [
05 00 01 28
05 00 01 10
];

disp_timings0: display-timings {
native-mode = <&dsi0_timing0>;
dsi0_timing0: timing0 {
clock-frequency = <57000000>;
hactive = <600>;
vactive = <1280>;
hsync-len = <28>;
hback-porch = <48>;
hfront-porch = <49>;
vsync-len = <2>;
vback-porch = <13>;
vfront-porch = <15>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};

ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi: endpoint {
remote-endpoint = <&dsi_out_panel>;
};
};
};
};

ports {
#address-cells = <1>;
#size-cells = <0>;

port@1 {
reg = <1>;
dsi_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi>;
};
};
};
};

&vopl_out_dsi {
status = "okay";
};

&dsi_in_vopl {
status = "okay";
};

&dsi_in_vopb {
status = "disabled";
};

&route_dsi {
status = "disabled";
connect = <&vopl_out_dsi>;
};

&i2c1 {
status = "okay";
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;

ilitek: ilitek@41 {
compatible = "tchip,ilitek";
reg = <0x41>;

ilitek,irq-gpio = <&gpio1 RK_PD0 IRQ_TYPE_LEVEL_HIGH>;
ilitek,reset-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;

ilitek,name = "ilitek_i2c";
};
};

&pinctrl {
lcd-panel {
lcd_backlight_en: lcd-backlight-en {
rockchip,pins =
<4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
};

lcd_panel_reset: lcd-panel-reset {
rockchip,pins =
<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

&hdmi_sound {
status = "disabled";
};

&i2s2 {
status = "disabled";
};

&hdmi {
status = "okay";
};

&hdmi_in_vopb {
status = "okay";
};

&route_hdmi {
status = "okay";
};

&hdmi_sound {
status = "okay";
};

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