Move cpu.zig to smp.zig and some other changes

kernel/acpi.zig

@@ -169,9 +169,9 @@ fn handleMADT(madt: *const SDT) void {
 
         const entry = data[2..size];
         switch (kind) {
-            0 => log.warn("unhandled LAPIC: {any}", .{entry}),
-            1 => apic.io_apics.append(@ptrCast(entry)) catch unreachable,
-            2 => apic.isos.append(@ptrCast(entry)) catch unreachable,
+            0 => {}, // log.warn("unhandled LAPIC: {any}", .{entry}),
+            1 => apic.io_apics.append(root.allocator, @ptrCast(entry)) catch unreachable,
+            2 => apic.isos.append(root.allocator, @ptrCast(entry)) catch unreachable,
             3 => log.warn("unhandled IO/APIC NMI source: {any}", .{entry}),
             4 => log.warn("unhandled LAPIC NMI: {any}", .{entry}),
             5 => log.warn("unhandled LAPIC Address Override: {any}", .{entry}),

kernel/apic.zig

@@ -2,7 +2,7 @@ const std = @import("std");
 const root = @import("root");
 const arch = @import("arch.zig");
 const vmm = @import("vmm.zig");
-const cpu = @import("cpu.zig");
+const smp = @import("smp.zig");
 const idt = @import("idt.zig");
 const pit = @import("pit.zig");
 
@@ -55,8 +55,8 @@ const ISO = extern struct {
     flags: u16 align(1),
 };
 
-pub var io_apics = std.ArrayList(*const IOAPIC).init(root.allocator);
-pub var isos = std.ArrayList(*const ISO).init(root.allocator);
+pub var io_apics: std.ArrayListUnmanaged(*const IOAPIC) = .{};
+pub var isos: std.ArrayListUnmanaged(*const ISO) = .{};
 
 pub fn init() void {
     // TODO: this is done by all cpu not just bsp, change that >:(
@@ -79,7 +79,7 @@ pub fn timerOneShot(us: u64, vector: u8) void {
 
     timerStop();
 
-    const ticks = us * (cpu.this().lapic_freq / 1000000);
+    const ticks = us * (smp.thisCpu().lapic_freq / 1000000);
 
     writeRegister(.lvt_timer, vector);
     writeRegister(.timer_divide, 0);
@@ -115,7 +115,7 @@ pub fn timerCalibrate() void {
     const final_tick = pit.getCurrentCount();
 
     const total_ticks: u64 = initial_tick - final_tick;
-    cpu.this().lapic_freq = (samples / total_ticks) * pit.dividend;
+    smp.thisCpu().lapic_freq = (samples / total_ticks) * pit.dividend;
 
     timerStop();
 }

kernel/gdt.zig

@@ -1,6 +1,5 @@
 const log = @import("std").log.scoped(.gdt);
 const SpinLock = @import("lock.zig").SpinLock;
-const TSS = @import("cpu.zig").TSS;
 
 const GDTEntry = packed struct {
     limit_low: u16 = 0,
@@ -24,6 +23,17 @@ const TSSDescriptor = packed struct {
     reserved: u32 = 0,
 };
 
+/// Task State Segment
+pub const TSS = extern struct {
+    reserved0: u32 align(1) = 0,
+    rsp: [3]u64 align(1),
+    reserved1: u64 align(1) = 0,
+    ist: [7]u64 align(1),
+    reserved2: u64 align(1) = 0,
+    reserved3: u16 align(1) = 0,
+    iopb: u16 align(1),
+};
+
 /// Global Descriptor Table
 const GDT = extern struct {
     null_entry: GDTEntry align(8),

kernel/idt.zig

@@ -1,6 +1,5 @@
 const std = @import("std");
 const arch = @import("arch.zig");
-const cpu = @import("cpu.zig");
 const log = std.log.scoped(.idt);
 
 pub const page_fault_vector = 0x0e;
@@ -10,7 +9,34 @@ const call_gate = 0b1000_1100;
 const trap_gate = 0b1000_1111;
 
 const InterruptStub = *const fn () callconv(.Naked) void;
-pub const InterruptHandler = *const fn (ctx: *cpu.Context) void;
+pub const InterruptHandler = *const fn (ctx: *Context) void;
+
+pub const Context = extern struct {
+    ds: u64,
+    es: u64,
+    rax: u64,
+    rbx: u64,
+    rcx: u64,
+    rdx: u64,
+    rsi: u64,
+    rdi: u64,
+    rbp: u64,
+    r8: u64,
+    r9: u64,
+    r10: u64,
+    r11: u64,
+    r12: u64,
+    r13: u64,
+    r14: u64,
+    r15: u64,
+    isr_vector: u64,
+    error_code: u64,
+    rip: u64,
+    cs: u64,
+    rflags: u64,
+    rsp: u64,
+    ss: u64,
+};
 
 /// Interrupt Descriptor Table Entry
 const IDTEntry = extern struct {
@@ -119,7 +145,7 @@ pub inline fn registerHandler(vector: u8, handler: InterruptHandler) void {
     isr[vector] = handler;
 }
 
-fn exceptionHandler(ctx: *cpu.Context) void {
+fn exceptionHandler(ctx: *Context) void {
     const vector = ctx.isr_vector;
     const cr2 = arch.readRegister("cr2");
     const cr3 = arch.readRegister("cr3");
@@ -193,7 +219,7 @@ fn makeStubHandler(vector: u8) InterruptStub {
     }.handler;
 }
 
-export fn interruptHandler(ctx: *cpu.Context) callconv(.C) void {
+export fn interruptHandler(ctx: *Context) callconv(.C) void {
     const handler = isr[ctx.isr_vector];
     handler(ctx);
 }

kernel/main.zig

@@ -12,7 +12,7 @@ const pmm = @import("pmm.zig");
 const vmm = @import("vmm.zig");
 const proc = @import("proc.zig");
 const sched = @import("sched.zig");
-const cpu = @import("cpu.zig");
+const smp = @import("smp.zig");
 const acpi = @import("acpi.zig");
 const apic = @import("apic.zig");
 const ps2 = @import("ps2.zig");
@@ -153,11 +153,11 @@ fn main() !void {
 
     acpi.init(); // TODO: change so it can be after cpu smh
 
-    proc.init(); // TODO + TSS
+    proc.init(); // TODO
     sched.init(); // TODO
     // TODO: threads <- with priority level ? <- have a list of thread based
     // on priority level and state (accoriding to https://wiki.osdev.org/Going_further_on_x86
-    cpu.init(); // TODO
+    smp.init(); // TODO
 
     apic.init(); // TODO: local apic timers for sched
     pit.init();

kernel/pit.zig

@@ -3,7 +3,7 @@
 const std = @import("std");
 const root = @import("root");
 const arch = @import("arch.zig");
-const cpu = @import("cpu.zig");
+const smp = @import("smp.zig");
 const idt = @import("idt.zig");
 const apic = @import("apic.zig");
 const SpinLock = @import("lock.zig").SpinLock;
@@ -98,7 +98,7 @@ pub var monotonic: timespec = .{};
 pub var realtime: timespec = .{};
 
 var timers_lock: SpinLock = .{};
-var armed_timers = std.ArrayList(*Timer).init(root.allocator);
+var armed_timers = std.ArrayList(*Timer).init(root.allocator); // TODO
 
 pub fn init() void {
     const boot_time = root.boot_time_request.response.?.boot_time;
@@ -107,7 +107,7 @@ pub fn init() void {
     setFrequency(timer_freq);
     const timer_vector = idt.allocVector();
     idt.registerHandler(timer_vector, timerHandler);
-    apic.setIRQRedirect(cpu.bsp_lapic_id, timer_vector, 0);
+    apic.setIRQRedirect(smp.bsp_lapic_id, timer_vector, 0);
 
     log.info("realtime: {}", .{realtime});
 }
@@ -134,7 +134,7 @@ pub fn getCurrentCount() u16 {
     return (@as(u16, @intCast(hi)) << 8) | lo;
 }
 
-fn timerHandler(ctx: *cpu.Context) void {
+fn timerHandler(ctx: *idt.Context) void {
     _ = ctx;
 
     defer apic.eoi();

kernel/proc.zig

@@ -1,30 +1,35 @@
 const std = @import("std");
-const cpu = @import("cpu.zig");
+const smp = @import("smp.zig");
+const idt = @import("idt.zig");
 const SpinLock = @import("lock.zig").SpinLock;
 
 // TODO: this needs a lot of work
 
 pub const pid_t = std.os.linux.pid_t;
 pub const fd_t = std.os.linux.fd_t;
-// pub const uid_t = std.os.linux.uid_t;
-// pub const gid_t = std.os.linux.gid_t;
-// pub const clock_t = std.os.linux.clock_t;
+pub const uid_t = std.os.linux.uid_t;
+pub const gid_t = std.os.linux.gid_t;
 
 pub const Process = struct {
     pid: pid_t,
     name: []u8,
     parent: ?*Process,
+    // cwd: // TODO
+    threads: std.ArrayListUnmanaged(*Thread) = .{}, // TODO: use linked list?
+    children: std.ArrayListUnmanaged(*Process) = .{},
     // ...
 };
 
+// TODO: extern ?
 pub const Thread = struct {
     self: *Thread, // TODO
     errno: usize,
 
     tid: u32,
     lock: SpinLock,
-    this_cpu: *cpu.CpuLocal,
+    this_cpu: *smp.CpuLocal,
     process: *Process,
+    ctx: idt.Context,
     // ...
 };
 

kernel/ps2.zig

@@ -2,7 +2,7 @@ const std = @import("std");
 const root = @import("root");
 const arch = @import("arch.zig");
 const idt = @import("idt.zig");
-const cpu = @import("cpu.zig");
+const smp = @import("smp.zig");
 const apic = @import("apic.zig");
 
 pub fn init() void {
@@ -28,7 +28,7 @@ pub fn init() void {
 
     const keyboard_vector = idt.allocVector();
     idt.registerHandler(keyboard_vector, keyboardHandler);
-    apic.setIRQRedirect(cpu.bsp_lapic_id, keyboard_vector, 1);
+    apic.setIRQRedirect(smp.bsp_lapic_id, keyboard_vector, 1);
 
     _ = arch.in(u8, 0x60);
 }
@@ -53,7 +53,7 @@ fn writeConfig(value: u8) void {
     write(0x60, value);
 }
 
-fn keyboardHandler(ctx: *cpu.Context) void {
+fn keyboardHandler(ctx: *idt.Context) void {
     _ = ctx;
     // TODO
     if (root.tty0) |tty| {

kernel/sched.zig

@@ -1,5 +1,5 @@
 const std = @import("std");
-const cpu = @import("cpu.zig");
+const smp = @import("smp.zig");
 const idt = @import("idt.zig");
 const rand = @import("rand.zig");
 const proc = @import("proc.zig");
@@ -26,6 +26,6 @@ pub inline fn currentThread() *Thread {
     );
 }
 
-fn schedHandler(ctx: *cpu.Context) void {
+fn schedHandler(ctx: *idt.Context) void {
     _ = ctx;
 }

kernel/cpu.zig → kernel/smp.zig

@@ -13,53 +13,16 @@ const SpinLock = @import("lock.zig").SpinLock;
 const log = std.log.scoped(.cpu);
 
 // TODO: use SYSENTER/SYSEXIT
+// TODO: use FSGSBASE
 // TODO: move asm to x86_64.zig?
 
-pub const Context = extern struct {
-    ds: u64,
-    es: u64,
-    rax: u64,
-    rbx: u64,
-    rcx: u64,
-    rdx: u64,
-    rsi: u64,
-    rdi: u64,
-    rbp: u64,
-    r8: u64,
-    r9: u64,
-    r10: u64,
-    r11: u64,
-    r12: u64,
-    r13: u64,
-    r14: u64,
-    r15: u64,
-    isr_vector: u64,
-    error_code: u64,
-    rip: u64,
-    cs: u64,
-    rflags: u64,
-    rsp: u64,
-    ss: u64,
-};
-
-/// Task State Segment
-pub const TSS = extern struct {
-    reserved0: u32 align(1) = 0,
-    rsp: [3]u64 align(1),
-    reserved1: u64 align(1) = 0,
-    ist: [7]u64 align(1),
-    reserved2: u64 align(1) = 0,
-    reserved3: u16 align(1) = 0,
-    iopb: u16 align(1),
-};
-
 pub const CpuLocal = struct {
     cpu_number: usize, // TODO: useless?
     // active: bool,
     // last_run_queue_index: u32,
     lapic_id: u32,
     lapic_freq: u64,
-    tss: TSS,
+    tss: gdt.TSS,
     idle_thread: *Thread,
     // tlb_shootdown_lock: SpinLock,
     // tlb_shootdown_done: SpinLock,
@@ -165,8 +128,8 @@ var cpus_started: usize = 0;
 // TODO
 // pub var sysenter: bool = false;
 pub var fpu_storage_size: usize = 0;
-pub var fpu_save: *const fn (*Context) void = undefined;
-pub var fpu_restore: *const fn (*Context) void = undefined;
+pub var fpu_save: *const fn (*idt.Context) void = undefined;
+pub var fpu_restore: *const fn (*idt.Context) void = undefined;
 
 var lapic_lock: SpinLock = .{};
 
@@ -196,6 +159,7 @@ pub fn init() void {
             cpu_local.idle_thread = idle_thread;
             setGsBase(@intFromPtr(idle_thread));
 
+            // TODO: is common_int_stack correct?
             const common_int_stack_phys = pmm.alloc(@divExact(stack_size, page_size), true) orelse unreachable;
             const common_int_stack = common_int_stack_phys + stack_size + vmm.hhdm_offset;
             cpu_local.tss.rsp[0] = common_int_stack;
@@ -229,7 +193,7 @@ pub fn init() void {
     }
 }
 
-pub fn this() *CpuLocal {
+pub fn thisCpu() *CpuLocal {
     const thread = sched.currentThread();
     // TODO: panic when calling this function with interrupts on or scheduling enabled
     return thread.this_cpu;
@@ -357,7 +321,7 @@ inline fn setGsBase(addr: u64) void {
     arch.wrmsr(0xc0000101, addr);
 }
 
-inline fn xsave(ctx: *Context) void {
+inline fn xsave(ctx: *idt.Context) void {
     asm volatile (
         \\xsave [%ctx]
         :
@@ -368,7 +332,7 @@ inline fn xsave(ctx: *Context) void {
     );
 }
 
-inline fn xrstor(ctx: *Context) void {
+inline fn xrstor(ctx: *idt.Context) void {
     asm volatile (
         \\xrstor %[ctx]
         :
@@ -379,7 +343,7 @@ inline fn xrstor(ctx: *Context) void {
     );
 }
 
-inline fn fxsave(ctx: *Context) void {
+inline fn fxsave(ctx: *idt.Context) void {
     asm volatile (
         \\fxsave %[ctx]
         :
@@ -388,7 +352,7 @@ inline fn fxsave(ctx: *Context) void {
     );
 }
 
-inline fn fxrstor(ctx: *Context) void {
+inline fn fxrstor(ctx: *idt.Context) void {
     asm volatile (
         \\fxrstor %[ctx]
         :