Implement bitwise operators in RISCV simd

Signed-off-by: Zoltan Herczeg [email protected]
Samsung · Jan 21, 2025 · c3a9bd3 · c3a9bd3
1 parent acf00db
commit c3a9bd3
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Showing 2 changed files with 21 additions and 13 deletions.
diff --git a/src/jit/SimdRiscvInl.h b/src/jit/SimdRiscvInl.h
@@ -373,6 +373,7 @@ static void emitUnarySIMD(sljit_compiler* compiler, Instruction* instr)
     case ByteCode::I8X16NegOpcode:
     case ByteCode::I8X16AbsOpcode:
     case ByteCode::I8X16PopcntOpcode:
+    case ByteCode::V128NotOpcode:
         srcType = SLJIT_SIMD_ELEM_8;
         dstType = SLJIT_SIMD_ELEM_8;
         break;
@@ -464,10 +465,6 @@ static void emitUnarySIMD(sljit_compiler* compiler, Instruction* instr)
         srcType = SLJIT_SIMD_FLOAT | SLJIT_SIMD_ELEM_32;
         dstType = SLJIT_SIMD_FLOAT | SLJIT_SIMD_ELEM_64;
         break;
-    case ByteCode::V128NotOpcode:
-        srcType = SLJIT_SIMD_ELEM_128;
-        dstType = SLJIT_SIMD_ELEM_128;
-        break;
     default:
         ASSERT_NOT_REACHED();
         break;
@@ -490,7 +487,7 @@ static void emitUnarySIMD(sljit_compiler* compiler, Instruction* instr)
     case ByteCode::F64X2ConvertLowI32X4UOpcode:
         break;
     case ByteCode::V128NotOpcode:
-        simdEmitTypedOp(compiler, srcType, SimdOp::vxor_vv, dst, args[0].arg, (0x1F), SimdOp::rmIsImm);
+        simdEmitTypedOp(compiler, srcType, SimdOp::vxor_vi, dst, args[0].arg, (0x1F), SimdOp::rmIsImm);
         break;
     case ByteCode::I8X16NegOpcode:
     case ByteCode::I16X8NegOpcode:
@@ -671,6 +668,10 @@ static void emitBinarySIMD(sljit_compiler* compiler, Instruction* instr)
     case ByteCode::I8X16MaxUOpcode:
     case ByteCode::I8X16AvgrUOpcode:
     case ByteCode::I8X16SwizzleOpcode:
+    case ByteCode::V128AndOpcode:
+    case ByteCode::V128OrOpcode:
+    case ByteCode::V128XorOpcode:
+    case ByteCode::V128AndnotOpcode:
         srcType = SLJIT_SIMD_ELEM_8;
         dstType = SLJIT_SIMD_ELEM_8;
         break;
@@ -799,13 +800,6 @@ static void emitBinarySIMD(sljit_compiler* compiler, Instruction* instr)
         srcType = SLJIT_SIMD_FLOAT | SLJIT_SIMD_ELEM_64;
         dstType = SLJIT_SIMD_FLOAT | SLJIT_SIMD_ELEM_64;
         break;
-    case ByteCode::V128AndOpcode:
-    case ByteCode::V128OrOpcode:
-    case ByteCode::V128XorOpcode:
-    case ByteCode::V128AndnotOpcode:
-        srcType = SLJIT_SIMD_ELEM_128;
-        dstType = SLJIT_SIMD_ELEM_128;
-        break;
     default:
         ASSERT_NOT_REACHED();
         break;
@@ -1034,6 +1028,8 @@ static void emitBinarySIMD(sljit_compiler* compiler, Instruction* instr)
         simdEmitTypedOp(compiler, srcType, SimdOp::vxor_vv, dst, args[0].arg, args[1].arg);
         break;
     case ByteCode::V128AndnotOpcode:
+        simdEmitTypedOp(compiler, srcType, SimdOp::vxor_vi, SLJIT_TMP_DEST_VREG, args[1].arg, (0x1F), SimdOp::rmIsImm);
+        simdEmitOp(compiler, SimdOp::vand_vv, dst, args[0].arg, SLJIT_TMP_DEST_VREG);
         break;
     case ByteCode::I8X16SwizzleOpcode:
         simdEmitSwizzle(compiler, srcType, dst, args[0].arg, args[1].arg);
@@ -1048,6 +1044,17 @@ static void emitBinarySIMD(sljit_compiler* compiler, Instruction* instr)
     }
 }
 
+static void simdEmitBitSelect(sljit_compiler* compiler, sljit_s32 rd, sljit_s32 rn, sljit_s32 rm, sljit_s32 ro)
+{
+    sljit_s32 tmp = SLJIT_TMP_DEST_FREG;
+
+    simdEmitVsetivli(compiler, SLJIT_SIMD_ELEM_8, 0);
+    simdEmitOp(compiler, SimdOp::vxor_vi, SLJIT_TMP_DEST_VREG, ro, (0x1F), SimdOp::rmIsImm);
+    simdEmitOp(compiler, SimdOp::vand_vv, SLJIT_TMP_DEST_VREG, SLJIT_TMP_DEST_VREG, rm);
+    simdEmitOp(compiler, SimdOp::vand_vv, rd, rn, ro);
+    simdEmitOp(compiler, SimdOp::vor_vv, rd, rd, SLJIT_TMP_DEST_VREG);
+}
+
 static void emitTernarySIMD(sljit_compiler* compiler, Instruction* instr)
 {
     Operand* operands = instr->operands();
@@ -1105,6 +1112,7 @@ static void emitTernarySIMD(sljit_compiler* compiler, Instruction* instr)
 
     switch (instr->opcode()) {
     case ByteCode::V128BitSelectOpcode:
+        simdEmitBitSelect(compiler, dst, args[0].arg, args[1].arg, args[2].arg);
         break;
     case ByteCode::I8X16RelaxedLaneSelectOpcode:
         break;

diff --git a/third_party/sljit b/third_party/sljit
+27 −27		.github/workflows/actions.yml
+1 −1		GNUmakefile
+24 −24		sljit_src/allocator_src/sljitExecAllocatorCore.c
+82 −70		sljit_src/sljitLir.c
+13 −2		sljit_src/sljitLir.h
+20 −3		sljit_src/sljitNativeARM_32.c
+2 −1		sljit_src/sljitNativeARM_64.c
+20 −3		sljit_src/sljitNativeARM_T2_32.c
+1 −1		sljit_src/sljitNativeLOONGARCH_64.c
+13 −3		sljit_src/sljitNativeMIPS_common.c
+1 −1		sljit_src/sljitNativePPC_common.c
+23 −11		sljit_src/sljitNativeRISCV_32.c
+85 −46		sljit_src/sljitNativeRISCV_64.c
+802 −323		sljit_src/sljitNativeRISCV_common.c
+9 −11		sljit_src/sljitNativeS390X.c
+1 −1		sljit_src/sljitNativeX86_32.c
+1 −1		sljit_src/sljitNativeX86_64.c
+1 −2		sljit_src/sljitNativeX86_common.c
+109 −36		test_src/sljitTest.c
+2 −0		test_src/sljitTestFloat.h
+89 −77		test_src/sljitTestSimd.h