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Silimate · Jan 7, 2025 · 0fb0208 · 0fb0208
1 parent d3bb8de
commit 0fb0208
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Showing 2 changed files with 14 additions and 14 deletions.
diff --git a/test/regression_vars.tcl b/test/regression_vars.tcl
@@ -137,6 +137,7 @@ record_sta_tests {
   report_checks_src_attr
   write_timing_model_scalar
   liberty_latch3
+  report_checks_json
 }
 
 define_test_group fast [group_tests all]
diff --git a/test/report_checks_json.ok b/test/report_checks_json.ok
@@ -10,21 +10,20 @@
   "source_path": [
     {
       "inst": "",
+      "cell": "counter",
       "src": "",
       "pin": "clk",
-      "nets": [
-        "clk"
-      ],
       "arrival": 0.000e+00,
+      "capacitance": 3.742e-15,
       "slew": 0.000e+00
     },
     {
       "inst": "_1415_",
       "cell": "sky130_fd_sc_hd__dfrtp_1",
       "src": "synthesis/tests/counter.v:22.3-28.6",
       "pin": "_1415_/CLK",
-      "nets": [
-        "clk"
+      "net": "clk",
+      "hier_pins": [
       ],
       "arrival": 0.000e+00,
       "slew": 0.000e+00
@@ -34,19 +33,20 @@
       "cell": "sky130_fd_sc_hd__dfrtp_1",
       "src": "synthesis/tests/counter.v:22.3-28.6",
       "pin": "_1415_/Q",
-      "nets": [
-        "mid"
+      "net": "mid",
+      "hier_pins": [
       ],
       "arrival": 3.296e-10,
+      "capacitance": 1.949e-15,
       "slew": 3.612e-11
     },
     {
       "inst": "_1416_",
       "cell": "sky130_fd_sc_hd__dfrtp_1",
       "src": "synthesis/tests/counter.v:22.3-28.6",
       "pin": "_1416_/D",
-      "nets": [
-        "mid"
+      "net": "mid",
+      "hier_pins": [
       ],
       "arrival": 3.296e-10,
       "slew": 3.612e-11
@@ -57,21 +57,20 @@
   "target_clock_path": [
     {
       "inst": "",
+      "cell": "counter",
       "src": "",
       "pin": "clk",
-      "nets": [
-        "clk"
-      ],
       "arrival": 0.000e+00,
+      "capacitance": 3.742e-15,
       "slew": 0.000e+00
     },
     {
       "inst": "_1416_",
       "cell": "sky130_fd_sc_hd__dfrtp_1",
       "src": "synthesis/tests/counter.v:22.3-28.6",
       "pin": "_1416_/CLK",
-      "nets": [
-        "clk"
+      "net": "clk",
+      "hier_pins": [
       ],
       "arrival": 0.000e+00,
       "slew": 0.000e+00