Updates from upstream

README.md

@@ -128,34 +128,24 @@ The Zlib library is an optional.  If CMake finds libz, OpenSTA can
 read Liberty, Verilog, SDF, SPF, and SPEF files compressed with gzip.
 
 CUDD is a binary decision diageram (BDD) package that is used to
-improve conditional timing arc handling. OpenSTA does not require it
-to be installed, but it improves constant propagation, power activity propagation
-and spice netlist generation if it is installed.
+improve conditional timing arc handling, constant propagation, power
+activity propagation and spice netlist generation.
 
 CUDD is available
-[here](https://www.davidkebo.com/source/cudd_versions/cudd-3.0.0.tar.gz)
-or [here](https://sourceforge.net/projects/cudd-mirror/).
+[here](https://github.com/davidkebo/cudd/blob/main/cudd_versions/cudd-3.0.0.tar.gz).
 
-Use the CUDD_DIR option to set the install directory of the CUDD
-library if it is not in one of the normal system install directories.
+Unpack and build CUDD.
 
 ```
-cmake -DCUDD_DIR=$HOME/stax/cudd-3.0.0 .."
-```
-
-When building CUDD you may use the `--prefix ` option to `configure` to
-install in a location other than the default (`/usr/local/lib`).
-```
-cd $HOME/cudd-3.0.0
-mkdir $HOME/cudd
-./configure --prefix $HOME/cudd
+tar xvfz cudd-3.0.0.tar.gz
+cd cudd-3.0.0
+./configure
 make
-make install
-
-cd <opensta>/build
-cmake .. -DUSE_CUDD=ON -DCUDD_DIR=$HOME/cudd
 ```
 
+You can use the "configure --prefix" option and "make install" to install CUDD
+in a different directory.
+
 ### Installing with CMake
 
 Use the following commands to checkout the git repository and build the
@@ -166,7 +156,7 @@ git clone https://github.com/parallaxsw/OpenSTA.git
 cd OpenSTA
 mkdir build
 cd build
-cmake ..
+cmake -DCUDD_DIR=<CUDD_INSTALL_DIR> ,.
 make
 ```
 The default build type is release to compile optimized code.
@@ -180,7 +170,7 @@ CMAKE_BUILD_TYPE DEBUG|RELEASE
 CMAKE_CXX_FLAGS - additional compiler flags
 TCL_LIBRARY - path to tcl library
 TCL_HEADER - path to tcl.h
-CUDD - path to cudd installation
+CUDD_DIR - path to cudd installation
 ZLIB_ROOT - path to zlib
 CMAKE_INSTALL_PREFIX
 ```
@@ -189,11 +179,7 @@ If `TCL_LIBRARY` is specified the CMake script will attempt to locate
 the header from the library path.
 
 The default install directory is `/usr/local`.
-To install in a different directory with CMake use:
-
-```
-cmake .. -DCMAKE_INSTALL_PREFIX=<prefix_path>
-```
+To install in a different directory with CMake use the CMAKE_INSTALL_PREFIX option.
 
 If you make changes to `CMakeLists.txt` you may need to clean out
 existing CMake cached variable values by deleting all of the

test/get_filter.tcl

@@ -1,3 +1,5 @@
+# Test get_* -filter
+
 # Read in design and libraries
 read_liberty asap7_small.lib.gz
 read_verilog reg1_asap7.v

test/liberty_arcs_one2one.lib → test/liberty_arcs_one2one_1.lib

@@ -1,4 +1,4 @@
-library (one_to_one_mismatched_width) {
+library (liberty_arcs_one2one_1) {
   delay_model : "table_lookup";
   simulation : false;
   capacitive_load_unit (1,pF);
@@ -47,34 +47,7 @@ library (one_to_one_mismatched_width) {
       direction : "output";
       timing () {
         related_pin : "A";
-        cell_rise (scalar) {
-          values ("1");
-        }
-        cell_fall (scalar) {
-          values ("1");
-        }
-        rise_transition (scalar) {
-          values ("1");
-        }
-        fall_transition (scalar) {
-          values ("1");
-        }
-      }
-    }
-  }
-
-  cell (inv_4_to_8) {
-    bus (A) {
-      capacitance : 1;
-      bus_type : "bus4";
-      direction : "input";
-    }
-    bus (Y) {
-      function : "!A";
-      bus_type : "bus8";
-      direction : "output";
-      timing () {
-        related_pin : "A";
+	timing_sense : "negative_unate";
         cell_rise (scalar) {
           values ("1");
         }

test/liberty_arcs_one2one_1.ok

@@ -0,0 +1,21 @@
+Warning: liberty_arcs_one2one_1.lib line 48, timing port A and related port Y are different sizes.
+report_edges -from partial_wide_inv_cell/A[0]
+A[0] -> Y[0] combinational
+  ^ -> v 1.00:1.00
+  v -> ^ 1.00:1.00
+report_edges -from partial_wide_inv_cell/A[1]
+A[1] -> Y[1] combinational
+  ^ -> v 1.00:1.00
+  v -> ^ 1.00:1.00
+report_edges -from partial_wide_inv_cell/A[2]
+A[2] -> Y[2] combinational
+  ^ -> v 1.00:1.00
+  v -> ^ 1.00:1.00
+report_edges -from partial_wide_inv_cell/A[3]
+A[3] -> Y[3] combinational
+  ^ -> v 1.00:1.00
+  v -> ^ 1.00:1.00
+report_edges -from partial_wide_inv_cell/A[4]
+report_edges -from partial_wide_inv_cell/A[5]
+report_edges -from partial_wide_inv_cell/A[6]
+report_edges -from partial_wide_inv_cell/A[7]

test/liberty_arcs_one2one_1.tcl

@@ -0,0 +1,11 @@
+# Test one-to-one functionality with mismatched widths where A width (8) is larger than Y width (4)
+read_liberty liberty_arcs_one2one_1.lib
+read_verilog liberty_arcs_one2one_1.v
+link_design liberty_arcs_one2one_1
+create_clock -name clk -period 0
+set_input_delay -clock clk 0 [all_inputs]
+set_output_delay -clock clk 0 [all_outputs]
+for {set i 0} {$i < 8} {incr i} {
+    puts "report_edges -from partial_wide_inv_cell/A[$i]"
+    report_edges -from partial_wide_inv_cell/A[$i]
+}