Update

dcalc/DelayCalc.i

@@ -59,8 +59,8 @@ report_delay_calc_cmd(Edge *edge,
 		      const MinMax *min_max,
 		      int digits)
 {
-  cmdLinkedNetwork();
-  return Sta::sta()->reportDelayCalc(edge, arc, corner, min_max, digits);
+  Sta *sta = Sta::sta();
+  return sta->reportDelayCalc(edge, arc, corner, min_max, digits);
 }
 
 void
@@ -77,7 +77,6 @@ set_prima_reduce_order(size_t order)
 void
 find_delays()
 {
-  cmdLinkedNetwork();
   Sta::sta()->findDelays();
 }
 

graph/Graph.i

@@ -27,13 +27,6 @@
 #include "Search.hh"
 #include "Sta.hh"
 
-namespace sta {
-
-Graph *
-cmdGraph();
-
-} // namespace
-
 using namespace sta;
 
 %}
@@ -85,25 +78,26 @@ private:
 int
 graph_vertex_count()
 {
-  return cmdGraph()->vertexCount();
+  return Sta::sta()->ensureGraph()->vertexCount();
 }
 
 int
 graph_edge_count()
 {
-  return cmdGraph()->edgeCount();
+  return Sta::sta()->ensureGraph()->edgeCount();
 }
 
 int
 graph_arc_count()
 {
-  return cmdGraph()->arcCount();
+  return Sta::sta()->ensureGraph()->arcCount();
 }
 
 VertexIterator *
 vertex_iterator()
 {
-  return new VertexIterator(cmdGraph());
+  Graph *graph = Sta::sta()->ensureGraph();
+  return new VertexIterator(graph);
 }
 
 void
@@ -113,7 +107,6 @@ set_arc_delay(Edge *edge,
 	      const MinMaxAll *min_max,
 	      float delay)
 {
-  cmdGraph();
   Sta::sta()->setArcDelay(edge, arc, corner, min_max, delay);
 }
 
@@ -124,15 +117,13 @@ set_annotated_slew(Vertex *vertex,
 		   const RiseFallBoth *rf,
 		   float slew)
 {
-  cmdGraph();
   Sta::sta()->setAnnotatedSlew(vertex, corner, min_max, rf, slew);
 }
 
 // Remove all delay and slew annotations.
 void
 remove_delay_slew_annotations()
 {
-  cmdGraph();
   Sta::sta()->removeDelaySlewAnnotations();
 }
 
@@ -422,7 +413,7 @@ latch_d_to_q_en()
 {
   if (self->role() == TimingRole::latchDtoQ()) {
     Sta *sta = Sta::sta();
-    const Network *network = sta->cmdNetwork();
+    const Network *network = sta->ensureLinked();
     const Graph *graph = sta->graph();
     Pin *from_pin = self->from(graph)->pin();
     Instance *inst = network->instance(from_pin);

include/sta/Network.hh

@@ -123,7 +123,7 @@ public:
   virtual void readLibertyAfter(LibertyLibrary *library);
   // First liberty library read is used to look up defaults.
   // This corresponds to a link_path of '*'.
-  LibertyLibrary *defaultLibertyLibrary() const;
+  virtual LibertyLibrary *defaultLibertyLibrary() const;
   void setDefaultLibertyLibrary(LibertyLibrary *library);
   // Check liberty cells used by the network to make sure they exist
   // for all the defined corners.

include/sta/SdcNetwork.hh

@@ -34,6 +34,7 @@ public:
 
   const char *name(const Library *library) const override;
   ObjectId id(const Library *library) const override;
+  LibertyLibrary *defaultLibertyLibrary() const override;
   LibraryIterator *libraryIterator() const override;
   LibertyLibraryIterator *libertyLibraryIterator() const override;
   Library *findLibrary(const char *name) override;

include/sta/Sta.hh

@@ -1196,7 +1196,7 @@ public:
   // disconnect_net
   virtual void disconnectPin(Pin *pin);
   virtual void makePortPin(const char *port_name,
-                           const char *direction);
+                           PortDirection *dir);
   // Notify STA of network change.
   void networkChanged();
   void deleteLeafInstanceBefore(const Instance *inst);
@@ -1236,6 +1236,8 @@ public:
 
   void setTclInterp(Tcl_Interp *interp);
   Tcl_Interp *tclInterp();
+  // Ensure a network has been read, linked and liberty libraries exist.
+  Network *ensureLinked();
   void ensureLevelized();
   // Ensure that the timing graph has been built.
   Graph *ensureGraph();
@@ -1293,24 +1295,6 @@ public:
                     const Corner *corner);
   PwrActivity findClkedActivity(const Pin *pin);
 
-  void writeGateSpice(ArcDcalcArgSeq gates,
-                      const char *spice_filename,
-                      const char *subckt_filename,
-                      const char *lib_subckt_filename,
-                      const char *model_filename,
-                      const char *power_name,
-                      const char *gnd_name,
-                      CircuitSim ckt_sim,
-                      const Corner *corner,
-                      const MinMax *min_max);
-  void writeGateGnuplot(ArcDcalcArgSeq gates,
-                        PinSet plot_pins,
-                        const char *spice_waveform_filename,
-                        const char *csv_filename,
-                        const char *gnuplot_filename,
-                        const Corner *corner,
-                        const MinMax *min_max);
-
   void writeTimingModel(const char *lib_name,
                         const char *cell_name,
                         const char *filename,
@@ -1323,6 +1307,15 @@ public:
 		      LibertyLibrarySeq *map_libs);
   LibertyCellSeq *equivCells(LibertyCell *cell);
 
+  void writePathSpice(PathRef *path,
+                      const char *spice_filename,
+                      const char *subckt_filename,
+                      const char *lib_subckt_filename,
+                      const char *model_filename,
+                      const char *power_name,
+                      const char *gnd_name,
+                      CircuitSim ckt_sim);
+
 protected:
   // Default constructors that are called by makeComponents in the Sta
   // constructor.  These can be redefined by a derived class to

liberty/Liberty.i

@@ -182,19 +182,19 @@ liberty_supply_exists(const char *supply_name)
 LibertyLibraryIterator *
 liberty_library_iterator()
 {
-  return cmdNetwork()->libertyLibraryIterator();
+  return Sta::sta()->network()->libertyLibraryIterator();
 }
 
 LibertyLibrary *
 find_liberty(const char *name)
 {
-  return cmdNetwork()->findLiberty(name);
+  return Sta::sta()->network()->findLiberty(name);
 }
 
 LibertyCell *
 find_liberty_cell(const char *name)
 {
-  return cmdNetwork()->findLibertyCell(name);
+  return Sta::sta()->network()->findLibertyCell(name);
 }
 
 bool

liberty/LibertyReader.cc

@@ -3963,21 +3963,29 @@ LibertyReader::seqPortNames(LibertyGroup *group,
 			    bool &has_size,
 			    int &size)
 {
-  int i = 0;
   out_name = nullptr;
   out_inv_name = nullptr;
   size = 1;
   has_size = false;
-  for (LibertyAttrValue *value : *group->params()) {
-    if (i == 0)
-      out_name = value->stringValue();
-    else if (i == 1)
-      out_inv_name = value->stringValue();
-    else if (i == 2) {
-      size = static_cast<int>(value->floatValue());
+  if (group->params()->size() == 2) {
+    // out_port, out_port_inv
+    out_name = group->firstName();
+    out_inv_name = group->secondName();
+  }
+  else if (group->params()->size() == 3) {
+    LibertyAttrValue *third_value = (*group->params())[2];
+    if (third_value->isFloat()) {
+      // out_port, out_port_inv, bus_size
+      out_name = group->firstName();
+      out_inv_name = group->secondName();
+      size = static_cast<int>(third_value->floatValue());
       has_size = true;
     }
-    i++;
+    else {
+      // in_port (ignored), out_port, out_port_inv
+      out_name = group->secondName();
+      out_inv_name = third_value->stringValue();
+    }
   }
 }