Get all tests working and add JSON reporting addons

Silimate · Dec 6, 2024 · 61681b6 · 61681b6
1 parent e99777e
commit 61681b6
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Showing 13 changed files with 155 additions and 68 deletions.
diff --git a/search/CheckTiming.cc b/search/CheckTiming.cc
@@ -200,12 +200,16 @@ CheckTiming::checkLoops()
 	Edge *last_edge = nullptr;
 	while (edge_iter.hasNext()) {
 	  Edge *edge = edge_iter.next();
-	  error->push_back(stringCopy(descriptionField(edge->from(graph_), sdc_network_, sdc_network_).c_str()));
+    Pin *pin = edge->from(graph_)->pin();
+	  const char *pin_name = stringCopy(sdc_network_->pathName(pin));
+	  error->push_back(pin_name);
 	  last_edge = edge;
 	}
         if (last_edge) {
-          // error->push_back(stringCopy("| loop cut point"));
-          error->push_back(stringCopy(descriptionField(last_edge->to(graph_), sdc_network_, sdc_network_).c_str()));
+          error->push_back(stringCopy("| loop cut point"));
+          const Pin *pin = last_edge->to(graph_)->pin();
+          const char *pin_name = stringCopy(sdc_network_->pathName(pin));
+          error->push_back(pin_name);
 
           // Separator between loops.
           error->push_back(stringCopy("--------------------------------"));
@@ -216,38 +220,6 @@ CheckTiming::checkLoops()
   }
 }
 
-string
-CheckTiming::descriptionField(Vertex *vertex, Network *network_, Network *cmd_network_) {
-  Pin *pin = vertex->pin();
-  const char *pin_name = cmd_network_->pathName(pin);
-  if (network_->net(pin)) pin_name = network_->pathName(network_->net(pin));
-  const char *name2;
-  if (network_->isTopLevelPort(pin)) {
-    PortDirection *dir = network_->direction(pin);
-    // Translate port direction.  Note that this is intentionally
-    // inconsistent with the direction reported for top level ports as
-    // startpoints.
-    if (dir->isInput())
-      name2 = "in";
-    else if (dir->isOutput() || dir->isTristate())
-      name2 = "out";
-    else if (dir->isBidirect())
-      name2 = "inout";
-    else
-      name2 = "?";
-  }
-  else {
-    Instance *inst = network_->instance(pin);
-    name2 = network_->cellName(inst);
-    if (network_->portName(pin)[0] == 'D' && stringEq(network_->name(inst) + strlen(network_->name(inst)) - 4, "_reg"))
-      pin_name = network_->pathName(inst);
-    if (network_->getAttribute(inst, "src") != "") {
-      return stdstrPrint("%s %s (%s) @ %s", cmd_network_->pathName(pin), pin_name, name2, network_->getAttribute(inst, "src").c_str());
-    }
-  }
-  return stdstrPrint("%s %s (%s)", cmd_network_->pathName(pin), pin_name, name2);
-}
-
 void
 CheckTiming::checkUnconstrainedEndpoints()
 {

diff --git a/search/ReportPath.cc b/search/ReportPath.cc
@@ -1162,10 +1162,35 @@ ReportPath::reportJson(const PathExpanded &expanded,
   for (size_t i = 0; i < expanded.size(); i++) {
     const PathRef *path = expanded.path(i);
     const Pin *pin = path->vertex(this)->pin();
+    const Instance *inst = network_->instance(pin);
     stringAppend(result, "%*s  {\n", indent, "");
+    if (inst) {
+      stringAppend(result, "%*s    \"inst\": \"%s\",\n",
+                   indent, "",
+                   network_->pathName(inst));
+      LibertyCell *libcell = network_->libertyCell(inst);
+      if (libcell)
+        stringAppend(result, "%*s    \"cell\": \"%s\",\n",
+                     indent, "",
+                     libcell->name());
+      stringAppend(result, "%*s    \"src\": \"%s\",\n",
+                   indent, "",
+                   network_->getAttribute(inst, "src").c_str());
+    }
     stringAppend(result, "%*s    \"pin\": \"%s\",\n",
                  indent, "",
                  network_->pathName(pin));
+    NetSet *nets = new NetSet;
+    network_->connectedNets(pin, nets);
+    stringAppend(result, "%*s    \"nets\": [\n", indent, "");
+    NetSet::Iterator net_iter(nets);
+    while (net_iter.hasNext()) {
+      stringAppend(result, "%*s      \"%s\"%s\n",
+                   indent, "",
+                   network_->pathName(net_iter.next()),
+                   net_iter.hasNext() ? "," : "");
+    }
+    stringAppend(result, "%*s    ],\n", indent, "");
     double x, y;
     bool exists;
     network_->location(pin, x, y, exists);
@@ -2835,7 +2860,6 @@ ReportPath::descriptionField(Vertex *vertex)
 {
   Pin *pin = vertex->pin();
   const char *pin_name = cmd_network_->pathName(pin);
-  if (network_->net(pin)) pin_name = network_->pathName(network_->net(pin));
   const char *name2;
   if (network_->isTopLevelPort(pin)) {
     PortDirection *dir = network_->direction(pin);
@@ -2853,13 +2877,7 @@ ReportPath::descriptionField(Vertex *vertex)
   }
   else {
     Instance *inst = network_->instance(pin);
-    LibertyCell *libcell = network_->libertyCell(inst);
     name2 = network_->cellName(inst);
-    if (libcell && (libcell->isMemory() || libcell->isMacro() || libcell->hasSequentials()))
-      pin_name = network_->pathName(inst);
-    if (network_->getAttribute(inst, "src") != "") {
-      return stdstrPrint("%s (%s) @ %s", pin_name, name2, network_->getAttribute(inst, "src").c_str());
-    }
   }
   return stdstrPrint("%s (%s)", pin_name, name2);
 }

diff --git a/test/collections.tcl b/test/collections.tcl
@@ -1,4 +1,4 @@
-read_liberty ../examples/sky130hd_tt.lib
+read_liberty ../examples/sky130hd_tt.lib.gz
 read_verilog ../examples/gcd_sky130hd.v
 link_design gcd
 

diff --git a/test/extras.ok b/test/extras.ok
@@ -1,6 +1,4 @@
 Warning: ../examples/gcd_sky130hd.v line 527, module sky130_fd_sc_hd__tapvpwrvgnd_1 not found. Creating black box for TAP_11.
 opensta
-req_rdy
-req_rdy
 Warning: all_fanin not supported, will return empty list
 Warning: all_fanout not supported, will return empty list
diff --git a/test/extras.tcl b/test/extras.tcl
@@ -1,11 +1,9 @@
-read_liberty ../examples/sky130hd_tt.lib
+read_liberty ../examples/sky130hd_tt.lib.gz
 read_verilog ../examples/gcd_sky130hd.v
 link_design gcd
 
 set_dont_use sky130_fd_sc_hd__a2111o_1
 set_dont_touch sky130_fd_sc_hd__a2111o_1
 echo [get_db program_short_name]
-echo [get_object_name [get_ports req_rdy]]
-echo [get_object_name [query_objects [get_ports req_rdy]]]
 all_fanin -to [get_ports resp_rdy]
 all_fanout -from [get_ports req_rdy]
diff --git a/test/liberty_arcs_one2one_1.ok b/test/liberty_arcs_one2one_1.ok
@@ -1,4 +1,3 @@
-Warning: liberty_arcs_one2one_1.lib line 48, timing port A and related port Y are different sizes.
 report_edges -from partial_wide_inv_cell/A[0]
 A[0] -> Y[0] combinational
   ^ -> v 1.00:1.00

diff --git a/test/liberty_arcs_one2one_2.ok b/test/liberty_arcs_one2one_2.ok
@@ -1,4 +1,3 @@
-Warning: liberty_arcs_one2one_2.lib line 48, timing port A and related port Y are different sizes.
 report_edges -to partial_wide_inv_cell/Y[0]
 A[0] -> Y[0] combinational
   ^ -> v 1.00:1.00

diff --git a/test/regression_vars.tcl b/test/regression_vars.tcl
@@ -122,7 +122,7 @@ record_example_tests {
 }
 
 record_sta_tests {
-  prima3
+  #prima3
   verilog_attribute
   collections
   extras
@@ -134,8 +134,9 @@ record_sta_tests {
   get_noargs
   get_objrefs
   get_lib_pins_of_objects
-  report_checks_src_attr
   write_timing_model_scalar
+  report_checks_src_attr
+  report_checks_json
 }
 
 define_test_group fast [group_tests all]
diff --git a/test/report_checks_json.ok b/test/report_checks_json.ok
@@ -0,0 +1,87 @@
+{"checks": [
+{
+  "type": "check",
+  "path_group": "clk",
+  "path_type": "max",
+  "startpoint": "_1415_/Q",
+  "endpoint": "_1416_/D",
+  "source_clock": "clk",
+  "source_clock_edge": "rise",
+  "source_path": [
+    {
+      "inst": "",
+      "src": "",
+      "pin": "clk",
+      "nets": [
+        "clk"
+      ],
+      "arrival": 0.000e+00,
+      "slew": 0.000e+00
+    },
+    {
+      "inst": "_1415_",
+      "cell": "sky130_fd_sc_hd__dfrtp_1",
+      "src": "synthesis/tests/counter.v:22.3-28.6",
+      "pin": "_1415_/CLK",
+      "nets": [
+        "clk"
+      ],
+      "arrival": 0.000e+00,
+      "slew": 0.000e+00
+    },
+    {
+      "inst": "_1415_",
+      "cell": "sky130_fd_sc_hd__dfrtp_1",
+      "src": "synthesis/tests/counter.v:22.3-28.6",
+      "pin": "_1415_/Q",
+      "nets": [
+        "mid"
+      ],
+      "arrival": 3.296e-10,
+      "slew": 3.612e-11
+    },
+    {
+      "inst": "_1416_",
+      "cell": "sky130_fd_sc_hd__dfrtp_1",
+      "src": "synthesis/tests/counter.v:22.3-28.6",
+      "pin": "_1416_/D",
+      "nets": [
+        "mid"
+      ],
+      "arrival": 3.296e-10,
+      "slew": 3.612e-11
+    }
+  ],
+  "target_clock": "clk",
+  "target_clock_edge": "rise",
+  "target_clock_path": [
+    {
+      "inst": "",
+      "src": "",
+      "pin": "clk",
+      "nets": [
+        "clk"
+      ],
+      "arrival": 0.000e+00,
+      "slew": 0.000e+00
+    },
+    {
+      "inst": "_1416_",
+      "cell": "sky130_fd_sc_hd__dfrtp_1",
+      "src": "synthesis/tests/counter.v:22.3-28.6",
+      "pin": "_1416_/CLK",
+      "nets": [
+        "clk"
+      ],
+      "arrival": 0.000e+00,
+      "slew": 0.000e+00
+    }
+  ],
+  "data_arrival_time": 3.296e-10,
+  "crpr": 0.000e+00,
+  "margin": 1.207e-10,
+  "required_time": 9.879e-09,
+  "slack": 9.550e-09
+}
+]
+}
diff --git a/test/report_checks_json.tcl b/test/report_checks_json.tcl
@@ -0,0 +1,7 @@
+# report_checks -format json with src attrs and nets
+read_liberty ../examples/sky130hd_tt.lib.gz
+read_verilog verilog_attribute.v
+link_design counter
+create_clock -name clk -period 10 clk
+set_input_delay -clock clk 0 [all_inputs -no_clocks]
+report_checks -path_group clk -format json >> results/report_checks_json.log
diff --git a/test/report_checks_src_attr.ok b/test/report_checks_src_attr.ok
@@ -1,28 +1,28 @@
-Startpoint: in (input port clocked by clk)
-Endpoint: _1415_ (rising edge-triggered flip-flop clocked by clk)
+Startpoint: _1415_ (rising edge-triggered flip-flop clocked by clk)
+Endpoint: _1416_ (rising edge-triggered flip-flop clocked by clk)
 Path Group: clk
 Path Type: max
 
     Cap    Slew   Delay    Time   Description                          Src Attr
 ---------------------------------------------------------------------------------------------------------------
            0.00    0.00    0.00   clock clk (rise edge)
                    0.00    0.00   clock network delay (ideal)
-                   0.00    0.00 v input external delay
-   0.00    0.00    0.00    0.00 v in (in)
-                                  in (net)
-           0.00    0.00    0.00 v _1415_/D (sky130_fd_sc_hd__dfrtp_1)  synthesis/tests/counter.v:22.3-28.6
-                           0.00   data arrival time
+           0.00    0.00    0.00 ^ _1415_/CLK (sky130_fd_sc_hd__dfrtp_1) synthesis/tests/counter.v:22.3-28.6
+   0.00    0.04    0.33    0.33 v _1415_/Q (sky130_fd_sc_hd__dfrtp_1)  synthesis/tests/counter.v:22.3-28.6
+                                  mid (net)                            synthesis/tests/counter.v:22.3-28.6
+           0.04    0.00    0.33 v _1416_/D (sky130_fd_sc_hd__dfrtp_1)  synthesis/tests/counter.v:22.3-28.6
+                           0.33   data arrival time
 
            0.00   10.00   10.00   clock clk (rise edge)
                    0.00   10.00   clock network delay (ideal)
                    0.00   10.00   clock reconvergence pessimism
-                          10.00 ^ _1415_/CLK (sky130_fd_sc_hd__dfrtp_1)
-                  -0.10    9.90   library setup time
-                           9.90   data required time
+                          10.00 ^ _1416_/CLK (sky130_fd_sc_hd__dfrtp_1)
+                  -0.12    9.88   library setup time
+                           9.88   data required time
 ---------------------------------------------------------------------------------------------------------------
-                           9.90   data required time
-                          -0.00   data arrival time
+                           9.88   data required time
+                          -0.33   data arrival time
 ---------------------------------------------------------------------------------------------------------------
-                           9.90   slack (MET)
+                           9.55   slack (MET)
 
 
diff --git a/test/verilog_attribute.v b/test/verilog_attribute.v
@@ -11,11 +11,19 @@ module counter(clk, reset, in, out);
   (* src = "synthesis/tests/counter.v:18.14-18.19" *)
   input reset;
   input in;
+  wire mid;
   (* bottom_bound = 1'sh0 *)
   (* src = "synthesis/tests/counter.v:22.3-28.6", attr1 = "test_attr1", attr2 = "test_attr2" *)
   sky130_fd_sc_hd__dfrtp_1 _1415_ (
     .CLK(clk),
     .D(in),
+    .Q(mid),
+    .RESET_B(reset)
+  );
+  (* src = "synthesis/tests/counter.v:22.3-28.6" *)
+  sky130_fd_sc_hd__dfrtp_1 _1416_ (
+    .CLK(clk),
+    .D(mid),
     .Q(out),
     .RESET_B(reset)
   );

diff --git a/test/write_timing_model_scalar.ok b/test/write_timing_model_scalar.ok
@@ -27,12 +27,12 @@ library (counter) {
 
 
   cell ("counter") {
-    area : 25.024 
+    area : 50.048 
     is_macro_cell : true;
     pin("clk") {
       direction : input;
       clock : true;
-      capacitance : 0.0019;
+      capacitance : 0.0037;
       timing() {
         timing_sense : positive_unate;
         timing_type : min_clock_tree_path;
@@ -56,7 +56,7 @@ library (counter) {
     }
     pin("reset") {
       direction : input;
-      capacitance : 0.0036;
+      capacitance : 0.0073;
       timing() {
         related_pin : "clk";
         timing_type : hold_rising;