Make is_memory property more sensitive for cells and libcells by al…

…so matching on `memory` groups (parallaxsw#129) * Add `has_memory` property * Whitespace fixes * Remove unused argument name * Review fixes * Move gf180mcu_sram.lib.gz from examples/ to test/ * Fix tcl script * Switch to is_memory * Remove is_memory_cell
Silimate · Nov 20, 2024 · 70d52c2 · 70d52c2
1 parent 3c461f2
commit 70d52c2
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Showing 10 changed files with 76 additions and 1 deletion.
diff --git a/doc/OpenSTA.odt b/doc/OpenSTA.odt
diff --git a/doc/OpenSTA.pdf b/doc/OpenSTA.pdf
diff --git a/liberty/LibertyReader.cc b/liberty/LibertyReader.cc
@@ -373,6 +373,10 @@ LibertyReader::defineVisitors()
                     &LibertyReader::visitLevelShifterDataPin);
   defineAttrVisitor("switch_pin", &LibertyReader::visitSwitchPin);
 
+  // Memory
+  defineGroupVisitor("memory", &LibertyReader::beginMemory,
+		     &LibertyReader::endMemory);
+
   // Register/latch
   defineGroupVisitor("ff", &LibertyReader::beginFF, &LibertyReader::endFF);
   defineGroupVisitor("ff_bank", &LibertyReader::beginFFBank,
@@ -3851,6 +3855,21 @@ LibertyReader::visitPortBoolAttr(LibertyAttr *attr,
 
 ////////////////////////////////////////////////////////////////
 
+void
+LibertyReader::beginMemory(LibertyGroup *)
+{
+  if (cell_) {
+    cell_->setIsMemory(true);
+  }
+}
+
+void
+LibertyReader::endMemory(LibertyGroup *)
+{
+}
+
+////////////////////////////////////////////////////////////////
+
 void
 LibertyReader::beginFF(LibertyGroup *group)
 {

diff --git a/liberty/LibertyReaderPvt.hh b/liberty/LibertyReaderPvt.hh
@@ -291,6 +291,9 @@ public:
   virtual void endWireloadSelection(LibertyGroup *group);
   virtual void visitWireloadFromArea(LibertyAttr *attr);
 
+  virtual void beginMemory(LibertyGroup *group);
+  virtual void endMemory(LibertyGroup *group);
+
   virtual void beginFF(LibertyGroup *group);
   virtual void endFF(LibertyGroup *group);
   virtual void beginFFBank(LibertyGroup *group);

diff --git a/search/Property.cc b/search/Property.cc
@@ -726,6 +726,8 @@ getProperty(const LibertyCell *cell,
     return PropertyValue(cell->isBuffer());
   else if (stringEqual(property, "is_inverter"))
     return PropertyValue(cell->isInverter());
+  else if (stringEqual(property, "is_memory"))
+    return PropertyValue(cell->isMemory());
   else if (stringEqual(property, "dont_use"))
     return PropertyValue(cell->dontUse());
   else if (stringEqual(property, "area"))
@@ -957,7 +959,7 @@ getProperty(const Instance *inst,
     return PropertyValue(liberty_cell && liberty_cell->isInverter());
   else if (stringEqual(property, "is_macro"))
     return PropertyValue(liberty_cell && liberty_cell->isMacro());
-  else if (stringEqual(property, "is_memory_cell"))
+  else if (stringEqual(property, "is_memory"))
     return PropertyValue(liberty_cell && liberty_cell->isMemory());
   else
     throw PropertyUnknown("instance", property);

diff --git a/test/get_is_memory.ok b/test/get_is_memory.ok
@@ -0,0 +1,4 @@
+[get_cells -filter is_memory]
+sram_inst
+[get_lib_cells -filter is_memory]
+gf180mcu_fd_ip_sram__sram128x8m8wm1__ff_125C_1v98/gf180mcu_fd_ip_sram__sram128x8m8wm1
diff --git a/test/get_is_memory.tcl b/test/get_is_memory.tcl
@@ -0,0 +1,11 @@
+# Tests whether the is_memory attribute works for cells and libcells
+read_liberty gf180mcu_sram.lib.gz
+read_liberty asap7_small.lib.gz
+read_verilog get_is_memory.v
+link get_is_memory
+
+# Test that the is_memory attribute is set correctly for cells
+puts {[get_cells -filter is_memory]}
+report_object_full_names [get_cells -filter is_memory]
+puts {[get_lib_cells -filter is_memory]}
+report_object_full_names [get_lib_cells -filter is_memory]
diff --git a/test/get_is_memory.v b/test/get_is_memory.v
@@ -0,0 +1,35 @@
+module get_is_memory (
+	input           CLK,
+	input           CEN,
+	input           GWEN,
+	input   [7:0]   WEN,
+	input   [6:0]   A,
+	input   [7:0]   D,
+	output  [7:0]   Q
+);
+
+	wire CEN_buf;
+	wire GWEN_reg;
+
+	BUFx2_ASAP7_75t_R buf_inst (
+		.A(CEN),
+		.Y(CEN_buf)
+	);
+
+	DFFHQx4_ASAP7_75t_R dff_inst (
+		.CLK(CLK),
+		.D(GWEN),
+		.Q(GWEN_reg)
+	);
+
+	gf180mcu_fd_ip_sram__sram128x8m8wm1 sram_inst (
+		.CLK(CLK),
+		.CEN(CEN_buf),
+		.GWEN(GWEN_reg),
+		.WEN(WEN),
+		.A(A),
+		.D(D),
+		.Q(Q)
+	);
+
+endmodule
diff --git a/test/gf180mcu_sram.lib.gz b/test/gf180mcu_sram.lib.gz
diff --git a/test/regression_vars.tcl b/test/regression_vars.tcl
@@ -126,6 +126,7 @@ record_sta_tests {
   verilog_attribute
   liberty_arcs_one2one_1
   liberty_arcs_one2one_2
+  get_is_memory
   get_filter
   get_noargs
   get_objrefs