Merge branch 'parallaxsw:master' into main

Dockerfile.centos7

@@ -19,13 +19,12 @@ RUN wget https://raw.githubusercontent.com/davidkebo/cudd/main/cudd_versions/cud
     tar -xvf cudd-3.0.0.tar.gz && \
     rm cudd-3.0.0.tar.gz
 
-# Install CUDD
+# Build CUDD
 RUN source /opt/rh/devtoolset-8/enable && \
     cd cudd-3.0.0 && \
     mkdir ../cudd && \
     ./configure && \
-    make -j`nproc` && \
-    make install
+    make -j`nproc`
 
 FROM base-dependencies AS builder
 
@@ -34,7 +33,10 @@ WORKDIR /OpenSTA
 
 # Build
 RUN rm -rf build && mkdir build
-RUN source /opt/rh/devtoolset-8/enable && cd build && cmake3 .. && make -j`nproc`
+RUN source /opt/rh/devtoolset-8/enable && \
+    cd build && \
+    cmake3 -DCUDD_DIR=../cudd-3.0.0 .. && \
+    make -j`nproc`
 
 # Run sta on entry
 ENTRYPOINT ["OpenSTA/app/sta"]

Dockerfile.ubuntu_18.04 → Dockerfile.ubuntu_22.04

@@ -1,23 +1,33 @@
-FROM ubuntu:18.04
+FROM ubuntu:22.04
 LABEL author="James Cherry"
 LABEL maintainer="James Cherry <[email protected]>"
 
 # Install basics
 ARG DEBIAN_FRONTEND=noninteractive
 RUN apt-get update && \
-    apt-get install -y wget cmake gcc tcl-dev tcl-tclreadline libeigen3-dev swig bison flex
+    apt-get install -y \
+    wget \
+    cmake \
+    gcc \
+    tcl-dev \
+    tcl-tclreadline \
+    libeigen3-dev \
+    swig \
+    bison \
+    flex \
+    automake \
+    autotools-dev
 
 # Download CUDD
 RUN wget https://raw.githubusercontent.com/davidkebo/cudd/main/cudd_versions/cudd-3.0.0.tar.gz && \
     tar -xvf cudd-3.0.0.tar.gz && \
     rm cudd-3.0.0.tar.gz
 
-# Install CUDD
+# Build CUDD
 RUN cd cudd-3.0.0 && \
     mkdir ../cudd && \
     ./configure && \
-    make -j`nproc` && \
-    make install
+    make -j`nproc`
 
 # Copy files and install OpenSTA
 RUN mkdir OpenSTA
@@ -26,7 +36,7 @@ RUN cd OpenSTA && \
     rm -rf build && \
     mkdir build && \
     cd build && \
-    cmake .. && \
+    cmake -DCUDD_DIR=../cudd-3.0.0 .. && \
     make -j`nproc`
 
 # Run sta on entry

README.md

@@ -9,6 +9,8 @@ standard file formats.
 * SDC timing constraints
 * SDF delay annotation
 * SPEF parasitics
+* VCD power acitivies
+* SAIF power acitivies
 
 OpenSTA uses a TCL command interpreter to read the design, specify
 timing constraints and print timing reports.
@@ -49,8 +51,8 @@ netlist data structures without duplicating them.
 * Simulator to propagate constants from constraints and netlist tie high/low
 
 See doc/OpenSTA.pdf for command documentation.
-See doc/StaApi.txt for timing engine API documentation.
 See doc/ChangeLog.txt for changes to commands.
+See doc/StaApi.txt for timing engine API documentation.
 
 OpenSTA is dual licensed. It is released under GPL v3 as OpenSTA and
 is also licensed for commerical applications by Parallax Software without

test/verilog_attribute.v

@@ -11,6 +11,7 @@ module counter(clk, reset, in, out);
   (* src = "synthesis/tests/counter.v:18.14-18.19" *)
   input reset;
   input in;
+  (* bottom_bound = 1'sh0 *)
   (* src = "synthesis/tests/counter.v:22.3-28.6", attr1 = "test_attr1", attr2 = "test_attr2" *)
   sky130_fd_sc_hd__dfrtp_1 _1415_ (
     .CLK(clk),

verilog/VerilogLex.ll

@@ -76,22 +76,22 @@ ID_TOKEN {ID_ESCAPED_TOKEN}|{ID_ALPHA_TOKEN}
 	}
 }
 
-{SIGN}?{UNSIGNED_NUMBER}?"'"[bB][01_xz]+ {
+{SIGN}?{UNSIGNED_NUMBER}?"'"[sS]?[bB][01_xz]+ {
   VerilogParse_lval.constant = sta::stringCopy(VerilogLex_text);
   return CONSTANT;
 }
 
-{SIGN}?{UNSIGNED_NUMBER}?"'"[oO][0-7_xz]+ {
+{SIGN}?{UNSIGNED_NUMBER}?"'"[sS]?[oO][0-7_xz]+ {
   VerilogParse_lval.constant = sta::stringCopy(VerilogLex_text);
   return CONSTANT;
 }
 
-{SIGN}?{UNSIGNED_NUMBER}?"'"[dD][0-9_]+ {
+{SIGN}?{UNSIGNED_NUMBER}?"'"[sS]?[dD][0-9_]+ {
   VerilogParse_lval.constant = sta::stringCopy(VerilogLex_text);
   return CONSTANT;
 }
 
-{SIGN}?{UNSIGNED_NUMBER}?"'"[hH][0-9a-fA-F_xz]+ {
+{SIGN}?{UNSIGNED_NUMBER}?"'"[sS]?[hH][0-9a-fA-F_xz]+ {
   VerilogParse_lval.constant = sta::stringCopy(VerilogLex_text);
   return CONSTANT;
 }