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issue146 verilog escaped nanes end in \n
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Signed-off-by: James Cherry <[email protected]>
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jjcherry56 committed Dec 20, 2024
1 parent a06c4fc commit 96b7e08
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion network/VerilogNamespace.cc
Original file line number Diff line number Diff line change
Expand Up @@ -180,7 +180,7 @@ verilogToSta(const char *verilog_name)
// Ignore leading '\'.
verilog_name = &verilog_name[1];
size_t verilog_name_length = strlen(verilog_name);
if (verilog_name[verilog_name_length - 1] == ' ')
if (isspace(verilog_name[verilog_name_length - 1]))
verilog_name_length--;
string sta_name;
for (size_t i = 0; i < verilog_name_length; i++) {
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