Merge upstream

include/sta/Sta.hh

@@ -917,6 +917,7 @@ public:
 		     PathEnd *prev_end,
                      bool last);
   void reportPathEnd(PathEnd *end);
+  void reportPathEnds(PathEndSeq *ends);
   ReportPath *reportPath() { return report_path_; }
   void reportPath(Path *path);
 

include/sta/StringUtil.hh

@@ -198,8 +198,5 @@ split(const string &text,
       const string &delims,
       // Return values.
       StringVector &tokens);
-
-std::string
-escapeBackslashes(const char *token);
 
 } // namespace

search/ReportPath.cc

@@ -335,14 +335,14 @@ void
 ReportPath::reportPathEnds(PathEndSeq *ends)
 {
   reportPathEndHeader();
-  PathEndSeq::Iterator end_iter(ends);
-  PathEnd *prev_end = nullptr;
-  while (end_iter.hasNext()) {
-    PathEnd *end = end_iter.next();
-    reportEndpointHeader(end, prev_end);
-    end->reportFull(this);
-    reportBlankLine();
-    prev_end = end;
+  if (ends) {
+    PathEndSeq::Iterator end_iter(ends);
+    PathEnd *prev_end = nullptr;
+    while (end_iter.hasNext()) {
+      PathEnd *end = end_iter.next();
+      reportPathEnd(end, prev_end, !end_iter.hasNext());
+      prev_end = end;
+    }
   }
   reportPathEndFooter();
 }
@@ -1095,9 +1095,9 @@ ReportPath::reportJson(const PathEnd *end,
   const Pin *startpoint = expanded.startPath()->vertex(this)->pin();
   const Pin *endpoint = expanded.endPath()->vertex(this)->pin();
   stringAppend(result, "  \"startpoint\": \"%s\",\n",
-               escapeBackslashes(network_->pathName(startpoint)).c_str());
+               sdc_network_->pathName(startpoint));
   stringAppend(result, "  \"endpoint\": \"%s\",\n",
-               escapeBackslashes(network_->pathName(endpoint)).c_str());
+               sdc_network_->pathName(endpoint));
 
   const ClockEdge *src_clk_edge = end->sourceClkEdge(this);
   const PathVertex *tgt_clk_path = end->targetClkPath();
@@ -1189,28 +1189,27 @@ ReportPath::reportJson(const PathExpanded &expanded,
     stringAppend(result, "%*s  {\n", indent, "");
 
     if (inst) {
-      stringAppend(result, "%*s    \"inst\": \"%s\",\n",
+      stringAppend(result, "%*s    \"instance\": \"%s\",\n",
                    indent, "",
-                   escapeBackslashes(network_->pathName(inst)).c_str());
+                   sdc_network_->pathName(inst));
       Cell *cell = network_->cell(inst);
       if (cell)
         stringAppend(result, "%*s    \"cell\": \"%s\",\n",
                      indent, "",
-                     escapeBackslashes(network_->name(cell)).c_str());
-      string src_string = network_->getAttribute(inst, "src");
-      stringAppend(result, "%*s    \"src\": \"%s\",\n",
+                     sdc_network_->name(cell));
+      stringAppend(result, "%*s    \"verilog_src\": \"%s\",\n",
                    indent, "",
-                   escapeBackslashes(src_string.c_str()).c_str());
+		   sdc_network_->getAttribute(inst, "src").c_str());
     }
 
     stringAppend(result, "%*s    \"pin\": \"%s\",\n",
                  indent, "",
-                 escapeBackslashes(network_->pathName(pin)).c_str());
+                 sdc_network_->pathName(pin));
 
     if (net) {
       stringAppend(result, "%*s    \"net\": \"%s\",\n",
                    indent, "",
-                   escapeBackslashes(network_->pathName(net)).c_str());
+                   sdc_network_->pathName(net));
     }
 
     PinSeq pins_above;
@@ -1219,9 +1218,9 @@ ReportPath::reportJson(const PathExpanded &expanded,
       stringAppend(result, "%*s    \"hier_pins\": [\n", indent, "");
       for (const Pin *hpin : pins_above) {
         stringAppend(result, "%*s      \"%s\"%s\n",
-                    indent, "",
-                    escapeBackslashes(network_->pathName(hpin)).c_str(),
-                    (hpin != pins_above.back()) ? "," : "");
+                     indent, "",
+                     sdc_network_->pathName(hpin),
+                     (hpin != pins_above.back()) ? "," : "");
       }
       stringAppend(result, "%*s    ],\n", indent, "");
     }

search/ReportPath.hh

@@ -38,6 +38,7 @@ class ReportPath : public StaState
 public:
   explicit ReportPath(StaState *sta);
   virtual ~ReportPath();
+  ReportPathFormat pathFormat() const { return format_; }
   void setPathFormat(ReportPathFormat format);
   void setReportFieldOrder(StringSeq *field_names);
   void setReportFields(bool report_input_pin,

search/Search.i

@@ -510,6 +510,18 @@ report_path_cmd(PathRef *path)
   Sta::sta()->reportPath(path);
 }
 
+void
+report_path_ends(PathEndSeq *ends)
+{
+  Sta *sta = Sta::sta();
+  Report *report = sta->report();
+  ReportPathFormat path_format = sta->reportPath()->pathFormat();
+  if (path_format == ReportPathFormat::json || (ends && ends->size() > 0))
+    sta->reportPathEnds(ends);
+  else
+    report->reportLine("No paths found.");
+}
+
 ////////////////////////////////////////////////////////////////
 
 void

search/Search.tcl

@@ -420,18 +420,9 @@ define_cmd_args "report_checks" \
 
 proc_redirect report_checks {
   global sta_report_unconstrained_paths
-
   parse_report_path_options "report_checks" args "full" 0
   set path_ends [find_timing_paths_cmd "report_checks" args]
-  if { $path_ends == {} } {
-    if { $format == "json" } {
-      report_line "{\"checks\" : \[\]}"
-    } else {
-      report_line "No paths found."
-    }
-  } else {
-    report_path_ends $path_ends
-  }
+  report_path_ends $path_ends
 }
 
 ################################################################
@@ -1097,19 +1088,6 @@ proc parse_path_group_arg { group_names } {
   return $names
 }
 
-proc report_path_ends { path_ends } {
-  report_path_end_header
-  set prev_end "NULL"
-  set end_count [llength $path_ends]
-  set i 0
-  foreach path_end $path_ends {
-    report_path_end2 $path_end $prev_end [expr $i == ($end_count - 1)]
-    set prev_end $path_end
-    incr i
-  }
-  report_path_end_footer
-}
-
 ################################################################
 
 define_cmd_args "report_clock_min_period" \

search/Sta.cc

@@ -2579,6 +2579,12 @@ Sta::reportPathEnd(PathEnd *end,
   report_path_->reportPathEnd(end, prev_end, last);
 }
 
+void
+Sta::reportPathEnds(PathEndSeq *ends)
+{
+  report_path_->reportPathEnds(ends);
+}
+
 void
 Sta::reportPath(Path *path)
 {

tcl/StaTclTypes.i

@@ -1286,6 +1286,10 @@ using namespace sta;
   Tcl_SetObjResult(interp, obj);
 }
 
+%typemap(in) PathEndSeq* {
+  $1 = tclListSeqPtr<PathEnd*>($input, SWIGTYPE_p_PathEnd, interp);
+}
+
 %typemap(out) PathEndSeq* {
   Tcl_Obj *list = Tcl_NewListObj(0, nullptr);
   const PathEndSeq *path_ends = $1;

test/regression_vars.tcl

@@ -136,8 +136,9 @@ record_sta_tests {
   get_lib_pins_of_objects
   report_checks_src_attr
   write_timing_model_scalar
+  report_json1
+  report_json2
   liberty_latch3
-  report_checks_json
 }
 
 define_test_group fast [group_tests all]

test/report_checks_src_attr.ok

@@ -1,5 +1,5 @@
 Startpoint: _1415_ (rising edge-triggered flip-flop clocked by clk)
-Endpoint: _1416_ (rising edge-triggered flip-flop clocked by clk)
+Endpoint: _1416_[0] (rising edge-triggered flip-flop clocked by clk)
 Path Group: clk
 Path Type: max
 
@@ -10,13 +10,13 @@ Path Type: max
            0.00    0.00    0.00 ^ _1415_/CLK (sky130_fd_sc_hd__dfrtp_1) synthesis/tests/counter.v:22.3-28.6
    0.00    0.04    0.33    0.33 v _1415_/Q (sky130_fd_sc_hd__dfrtp_1)  synthesis/tests/counter.v:22.3-28.6
                                   mid (net)                            synthesis/tests/counter.v:22.3-28.6
-           0.04    0.00    0.33 v _1416_/D (sky130_fd_sc_hd__dfrtp_1)  synthesis/tests/counter.v:22.3-28.6
+           0.04    0.00    0.33 v _1416_[0]/D (sky130_fd_sc_hd__dfrtp_1) synthesis/tests/counter.v:22.3-28.6
                            0.33   data arrival time
 
            0.00   10.00   10.00   clock clk (rise edge)
                    0.00   10.00   clock network delay (ideal)
                    0.00   10.00   clock reconvergence pessimism
-                          10.00 ^ _1416_/CLK (sky130_fd_sc_hd__dfrtp_1)
+                          10.00 ^ _1416_[0]/CLK (sky130_fd_sc_hd__dfrtp_1)
                   -0.12    9.88   library setup time
                            9.88   data required time
 ---------------------------------------------------------------------------------------------------------------

test/report_json1.ok

@@ -0,0 +1,78 @@
+{"checks": [
+{
+  "type": "check",
+  "path_group": "clk",
+  "path_type": "max",
+  "startpoint": "_1415_/Q",
+  "endpoint": "_1416_[0]/D",
+  "source_clock": "clk",
+  "source_clock_edge": "rise",
+  "source_path": [
+    {
+      "instance": "",
+      "cell": "counter",
+      "verilog_src": "",
+      "pin": "clk",
+      "arrival": 0.000e+00,
+      "capacitance": 3.742e-15,
+      "slew": 0.000e+00
+    },
+    {
+      "instance": "_1415_",
+      "cell": "sky130_fd_sc_hd__dfrtp_1",
+      "verilog_src": "synthesis/tests/counter.v:22.3-28.6",
+      "pin": "_1415_/CLK",
+      "net": "clk",
+      "arrival": 0.000e+00,
+      "slew": 0.000e+00
+    },
+    {
+      "instance": "_1415_",
+      "cell": "sky130_fd_sc_hd__dfrtp_1",
+      "verilog_src": "synthesis/tests/counter.v:22.3-28.6",
+      "pin": "_1415_/Q",
+      "net": "mid",
+      "arrival": 3.296e-10,
+      "capacitance": 1.949e-15,
+      "slew": 3.612e-11
+    },
+    {
+      "instance": "_1416_[0]",
+      "cell": "sky130_fd_sc_hd__dfrtp_1",
+      "verilog_src": "synthesis/tests/counter.v:22.3-28.6",
+      "pin": "_1416_[0]/D",
+      "net": "mid",
+      "arrival": 3.296e-10,
+      "slew": 3.612e-11
+    }
+  ],
+  "target_clock": "clk",
+  "target_clock_edge": "rise",
+  "target_clock_path": [
+    {
+      "instance": "",
+      "cell": "counter",
+      "verilog_src": "",
+      "pin": "clk",
+      "arrival": 0.000e+00,
+      "capacitance": 3.742e-15,
+      "slew": 0.000e+00
+    },
+    {
+      "instance": "_1416_[0]",
+      "cell": "sky130_fd_sc_hd__dfrtp_1",
+      "verilog_src": "synthesis/tests/counter.v:22.3-28.6",
+      "pin": "_1416_[0]/CLK",
+      "net": "clk",
+      "arrival": 0.000e+00,
+      "slew": 0.000e+00
+    }
+  ],
+  "data_arrival_time": 3.296e-10,
+  "crpr": 0.000e+00,
+  "margin": 1.207e-10,
+  "required_time": 9.879e-09,
+  "slack": 9.550e-09
+}
+]
+}

test/report_json1.tcl

@@ -0,0 +1,7 @@
+# report_checks -format json
+read_liberty ../examples/sky130hd_tt.lib.gz
+read_verilog verilog_attribute.v
+link_design counter
+create_clock -name clk -period 10 clk
+set_input_delay -clock clk 0 [all_inputs -no_clocks]
+report_checks -path_group clk -format json >> results/report_json1.log

test/report_json2.ok

@@ -0,0 +1,3 @@
+{"checks": [
+]
+}

test/report_json2.tcl

@@ -0,0 +1,6 @@
+# report_checks -format json with no paths
+read_liberty ../examples/sky130hd_tt.lib.gz
+read_verilog verilog_attribute.v
+link_design counter
+create_clock -name clk -period 10
+report_checks -path_group clk -format json >> results/report_json2.log

test/verilog_attribute.v

@@ -21,7 +21,7 @@ module counter(clk, reset, in, out);
     .RESET_B(reset)
   );
   (* src = "synthesis/tests/counter.v:22.3-28.6" *)
-  sky130_fd_sc_hd__dfrtp_1 _1416_ (
+  sky130_fd_sc_hd__dfrtp_1 \_1416_[0] (
     .CLK(clk),
     .D(mid),
     .Q(out),

util/StringUtil.cc

@@ -260,18 +260,5 @@ split(const string &text,
     tokens.push_back(text.substr(start));
 }
 
-std::string
-escapeBackslashes(const char *token)
-{
-  std::string escaped;
-  for (const char *s = token; *s; s++) {
-    char ch = *s;
-    if (ch == '\\')
-      escaped += '\\';
-    escaped += ch;
-  }
-  return escaped;
-}
-
 
 } // namespace