Merge branch 'parallaxsw:master' into main

Silimate · Oct 21, 2024 · cd06ff6 · cd06ff6
2 parents e8556b7 + 2218351
commit cd06ff6
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Showing 3 changed files with 21 additions and 18 deletions.
diff --git a/liberty/LibertyReader.cc b/liberty/LibertyReader.cc
@@ -3089,7 +3089,7 @@ LibertyReader::visitCellUserFunctionClass(LibertyAttr *attr)
   if (cell_) {
     const char *user_function_class = getAttrString(attr);
     if (user_function_class)
-      cell_->setUserFunctionClass(stringCopy(user_function_class));
+      cell_->setUserFunctionClass(user_function_class);
   }
 }
 

diff --git a/test/regression.tcl b/test/regression.tcl
@@ -285,6 +285,7 @@ proc run_test_plain { test cmd_file log_file } {
       cleanse_logfile $test $log_file
       return "ERROR $error"
     }
+    file delete $run_file
     cleanse_logfile $test $log_file
     return ""
   }

diff --git a/verilog/VerilogWriter.cc b/verilog/VerilogWriter.cc
@@ -411,30 +411,32 @@ VerilogWriter::writeAssigns(Instance *inst)
   while (pin_iter->hasNext()) {
     Pin *pin = pin_iter->next();
     Term *term = network_->term(pin);
-    Net *net = network_->net(term);
-    Port *port = network_->port(pin);
-    if (port
-        && (include_pwr_gnd_
-            || !(network_->isPower(net) || network_->isGround(net)))
-        && (network_->direction(port)->isAnyOutput()
-            || (include_pwr_gnd_ && network_->direction(port)->isPowerGround()))
-        && !stringEqual(network_->name(port), network_->name(net))) {
-      // Port name is different from net name.
-      string port_vname = netVerilogName(network_->name(port),
-                                         network_->pathEscape());
-      string net_vname = netVerilogName(network_->name(net),
-                                        network_->pathEscape());
-      fprintf(stream_, " assign %s = %s;\n",
-              port_vname.c_str(),
-              net_vname.c_str());
+    if (term) {
+      Net *net = network_->net(term);
+      Port *port = network_->port(pin);
+      if (port
+          && (include_pwr_gnd_
+              || !(network_->isPower(net) || network_->isGround(net)))
+          && (network_->direction(port)->isAnyOutput()
+              || (include_pwr_gnd_ && network_->direction(port)->isPowerGround()))
+          && !stringEqual(network_->name(port), network_->name(net))) {
+        // Port name is different from net name.
+        string port_vname = netVerilogName(network_->name(port),
+                                           network_->pathEscape());
+        string net_vname = netVerilogName(network_->name(net),
+                                          network_->pathEscape());
+        fprintf(stream_, " assign %s = %s;\n",
+                port_vname.c_str(),
+                net_vname.c_str());
+      }
     }
   }
   delete pin_iter;
 }
 
 ////////////////////////////////////////////////////////////////
 
-// Walk the hierarch counting unconnected nets used to connect to
+// Walk the hierarchy counting unconnected nets used to connect to
 // bus ports with concatenation.
 int
 VerilogWriter::findUnconnectedNetCount()