usb_device.rst incorrect UVM for REG_INTERRUPT

SpinalHDL · Aug 25, 2023 · fa08ad0 · fa08ad0
1 parent c549d23
commit fa08ad0
Showing 1 changed file with 18 additions and 17 deletions.
diff --git a/source/SpinalHDL/Libraries/Com/usb_device.rst b/source/SpinalHDL/Libraries/Com/usb_device.rst
@@ -81,23 +81,24 @@ finalise the SET_ADDRESS sequance. The controller will then automaticaly turn on
 INTERRUPT (0xFF08)
 **********************
 
-All bits of this register can be cleared by writing '1' in them.
-
-+--------------+------+-----------+------------------------------------------------------------------+
-| Name         | Type | Bits      | Description                                                      |
-+==============+======+===========+==================================================================+
-| endpoints    |  RC  | 15-0      | Raised when an endpoint generates an interrupt                   |
-+--------------+------+-----------+------------------------------------------------------------------+
-| reset        |  RC  | 16        | Raised when a USB reset occurs                                   |
-+--------------+------+-----------+------------------------------------------------------------------+
-| ep0Setup     |  RC  | 17        | Raised when endpoint 0 receives a setup transaction              |
-+--------------+------+-----------+------------------------------------------------------------------+
-| suspend      |  RC  | 18        | Raised when a USB suspend occurs                                 |
-+--------------+------+-----------+------------------------------------------------------------------+
-| resume       |  RC  | 19        | Raised when a USB resume occurs                                  |
-+--------------+------+-----------+------------------------------------------------------------------+
-| disconnect   |  RC  | 20        | Raised when a USB disconnect occurs                              |
-+--------------+------+-----------+------------------------------------------------------------------+
+Individual bits of this register can be cleared by writing '1' in them.
+Reading this register returns the current interrupt status.
+
++--------------+-------+-----------+------------------------------------------------------------------+
+| Name         | Type  | Bits      | Description                                                      |
++==============+=======+===========+==================================================================+
+| endpoints    |  W1C  | 15-0      | Raised when an endpoint generates an interrupt                   |
++--------------+-------+-----------+------------------------------------------------------------------+
+| reset        |  W1C  | 16        | Raised when a USB reset occurs                                   |
++--------------+-------+-----------+------------------------------------------------------------------+
+| ep0Setup     |  W1C  | 17        | Raised when endpoint 0 receives a setup transaction              |
++--------------+-------+-----------+------------------------------------------------------------------+
+| suspend      |  W1C  | 18        | Raised when a USB suspend occurs                                 |
++--------------+-------+-----------+------------------------------------------------------------------+
+| resume       |  W1C  | 19        | Raised when a USB resume occurs                                  |
++--------------+-------+-----------+------------------------------------------------------------------+
+| disconnect   |  W1C  | 20        | Raised when a USB disconnect occurs                              |
++--------------+-------+-----------+------------------------------------------------------------------+
 
 HALT (0xFF0C)
 **********************