sram rv working, some pycodestyle

StanfordAHA · Jan 17, 2025 · 54edde0 · 54edde0
1 parent 20fa645
commit 54edde0
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Showing 3 changed files with 5 additions and 10 deletions.
diff --git a/lake/modules/mu2f_io_core.py b/lake/modules/mu2f_io_core.py
@@ -194,7 +194,6 @@ def __init__(self,
                 self.wire(mu2io_r_0, kts.ternary(self._tile_en & self._clk_en, ~mu2io_2_io2f_fifo_0.ports.full, kts.const(0, 1)))
                 self.wire(mu2io_r_1, kts.ternary(self._tile_en & self._clk_en, ~mu2io_2_io2f_fifo_1.ports.full, kts.const(0, 1)))
 
-
         ########################################
         # TRACK SELECT
         ########################################
@@ -207,7 +206,6 @@ def __init__(self,
             self._tmp_track_active = self.input(f"track_active_T{track_num}", 1)
             self._tmp_track_active.add_attribute(ConfigRegAttr("Track active config register. States whether track is active."))
 
-
             # Create track output and its valid interface
             tmp_track_out = self.output(f"io2f_{tile_array_data_width}_T{track_num}", tile_array_data_width)
             tmp_track_out.add_attribute(ControlSignalAttr(is_control=False, full_bus=True))
@@ -292,7 +290,6 @@ def get_bitstream(self, config_dict):
         if 'track_active_T4' in config_dict:
             track_active_T4_val = config_dict['track_active_T4']
 
-
         config += [("track_select_T0", track_select_T0_val), ("track_select_T1", track_select_T1_val),
                     ("track_select_T2", track_select_T2_val), ("track_select_T3", track_select_T3_val),
                     ("track_select_T4", track_select_T4_val)]

diff --git a/lake/modules/onyx_pe.py b/lake/modules/onyx_pe.py
@@ -57,10 +57,9 @@ def __init__(self,
         self._active_inputs_encoding = self.input("active_inputs_encoding", 3)
         self._active_inputs_encoding.add_attribute(ConfigRegAttr("Sparse num inputs for rv/eos logic"))
 
-        # Is this a constant PE? 
+        # Is this a constant PE?
         self._is_constant_pe = self.input("is_constant_pe", 1)
         self._is_constant_pe.add_attribute(ConfigRegAttr("Is this PE outputting a constant value? (i.e. no inputs)"))
-
 
         gclk = self.var("gclk", 1)
         self._gclk = kts.util.clock(gclk)
@@ -284,7 +283,7 @@ def fifo_push():
             self._infifo_pop[0] = 0
             self._infifo_pop[1] = 0
             self._infifo_pop[2] = 0
-         
+
             # If this is a constant PE, push constant value to output FIFO indefinitely
             if self._is_constant_pe & ~self._dense_mode:
                 self._outfifo_push = 1
@@ -349,14 +348,13 @@ def get_bitstream(self, config_kwargs):
             active_inputs_encoding = config_kwargs['active_inputs']
         elif 'num_sparse_inputs' in config_kwargs:
             active_inputs_encoding = config_kwargs['num_sparse_inputs']
-            
+
         config += [('active_inputs_encoding', active_inputs_encoding)]
 
         if 'is_constant_pe' in config_kwargs:
             is_constant_pe = config_kwargs['is_constant_pe']
         config += [('is_constant_pe', is_constant_pe)]
 
-
         if 'use_dense' in config_kwargs and config_kwargs['use_dense'] is True:
             config += [("dense_mode", 1)]
         elif 'pe_connected_to_reduce' in config_kwargs and config_kwargs['pe_connected_to_reduce'] is True:

diff --git a/lake/modules/strg_RAM_rv.py b/lake/modules/strg_RAM_rv.py
@@ -219,7 +219,8 @@ def __init__(self,
         data_out = self._data_outfifo_data_in
         data_ready_in = ~self._data_outfifo_full
 
-        all_in_valid = ren_valid_in & rd_addr_valid_in
+        # all_in_valid = ren_valid_in & rd_addr_valid_in
+        all_in_valid = rd_addr_valid_in
 
         # Separate addressing...
         self.bit_range = (self.data_width - 1, 0)
@@ -259,7 +260,6 @@ def __init__(self,
         self._wr_addr_to_strg = self.output("wr_addr_to_strg", self.mem_addr_width)
         self.wire(self._wr_addr_to_strg, kts.const(0, self._wr_addr_to_strg.width))
 
-
         self.base_ports = [[None]]
         rw_port = MemoryPort(MemoryPortType.READWRITE)
         rw_port_intf = rw_port.get_port_interface()