config for conv_2_1 to spit out early data

StanfordAHA · Jan 10, 2025 · 923a4b3 · 923a4b3
1 parent 984685e
commit 923a4b3
Show file tree

Hide file tree

Showing 4 changed files with 17 additions and 9 deletions.
diff --git a/lake/modules/stencil_valid.py b/lake/modules/stencil_valid.py
@@ -87,9 +87,6 @@ def get_bitstream(self, config_json):
         Pass in a config-related json to return a list of
         (config_reg, value) tuples
         '''
-        # HACK: REMOVE BEFORE FLIGHT
-        config_json['stencil_valid']['cycle_stride'] = [1, 74]
-        config_json['stencil_valid']['extent'] = [74, 63]
         config = []
         stencil_valid = map_controller(extract_controller_json(config_json['stencil_valid']), "stencil_valid")
         config.append((f"stencil_valid_sched_gen_enable", 1))

diff --git a/lake/spec/iteration_domain.py b/lake/spec/iteration_domain.py
@@ -9,7 +9,7 @@
 class IterationDomain(Component):
 
     def __init__(self, dimensionality=6, extent_width=16):
-        super().__init__(f"for_loop_{dimensionality}_{extent_width}")
+        super().__init__(f"for_loop_{dimensionality}_{extent_width}_flush")
         self.dimensionality_support = dimensionality
         self.extent_width = extent_width
         self._interfaces = {}
@@ -132,6 +132,14 @@ def gen_hardware(self, pos_reset=False):
         self.config_space_fixed = True
         self._assemble_cfg_memory_input()
 
+        # if self.add_flush:
+        if True:
+            self.add_attribute("sync-reset=flush")
+            kts.passes.auto_insert_sync_reset(self.internal_generator)
+            # flush_port = self.internal_generator.get_port("flush")
+            # flush_port.add_attribute(ControlSignalAttr(True))
+
+
     @always_comb
     # Find lowest ready
     def set_mux_sel(self):

diff --git a/lake/spec/spec.py b/lake/spec/spec.py
@@ -1031,7 +1031,9 @@ def get_conv_2_1_app(self):
                 'extents': [in_size],
                 'address': {
                     'strides': [1],
-                    'offset': 0
+                    # 'offset': 0
+                    # Start this here to handle the bogus data creation
+                    'offset': 64
                 },
                 'schedule': {
                     'strides': [4],
@@ -1132,7 +1134,8 @@ def get_conv_2_1_app(self):
         pw_raw_idx = 0
         raw_comp = LFComparisonOperator.LT.value
         # raw_scalar = 4
-        raw_scalar = 64
+        # Allows the reads to start early
+        raw_scalar = -64
         raw_constraint = (pr, pr_raw_idx, pw, pw_raw_idx, raw_comp, raw_scalar)
 
         pw_war_idx = 0

diff --git a/lake/top/memtile_builder.py b/lake/top/memtile_builder.py
@@ -1338,7 +1338,7 @@ def get_bitstream(self, config_json):
                     # Handle low chunk
                     tmp_val = tmp_cfg_space[chunk_lo]
                     for z_ in range(num_bits_lo):
-                        print(f"Get bit at {z_}")
+                        # print(f"Get bit at {z_}")
                         tmp_val = self.set_bit(tmp_val, z_ + bits_lo, self.get_bit(val_int, z_))
                     tmp_cfg_space[chunk_lo] = tmp_val
 
@@ -1348,15 +1348,15 @@ def get_bitstream(self, config_json):
                         curr_chunk = chunk_lo + 1 + int_chk
                         tmp_val = tmp_cfg_space[curr_chunk]
                         for z_ in range(self.allowed_reg_size):
-                            print(f"Get bit at {(int_chk * self.allowed_reg_size) + num_bits_lo + z_}")
+                            # print(f"Get bit at {(int_chk * self.allowed_reg_size) + num_bits_lo + z_}")
                             tmp_val = self.set_bit(tmp_val, z_, self.get_bit(val_int, (int_chk * self.allowed_reg_size) + num_bits_lo + z_))
                         tmp_cfg_space[curr_chunk] = tmp_val
                         int_chk += 1
 
                     # Handle high chunk
                     tmp_val = tmp_cfg_space[chunk_hi]
                     for z_ in range(bits_hi):
-                        print(f"Get bit at {bits_intermed + num_bits_lo + z_}")
+                        # print(f"Get bit at {bits_intermed + num_bits_lo + z_}")
                         tmp_val = self.set_bit(tmp_val, z_, self.get_bit(val_int, bits_intermed + num_bits_lo + z_))
                     tmp_cfg_space[chunk_hi] = tmp_val