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Heartbeat feature #32
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Original file line number | Diff line number | Diff line change |
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@@ -586,7 +586,7 @@ int main() | |
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// Enable watchdog | ||
printf("Watchdog init\n\r"); | ||
AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDRSTEN | 0xFF00FF; // 1s | ||
AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDRSTEN | 0x7d007d0; | ||
AT91C_BASE_WDTC->WDTC_WDCR = 1 | 0xA5000000; | ||
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LED_off(0); | ||
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@@ -655,7 +655,8 @@ int main() | |
// Driver loop | ||
while (1) | ||
{ | ||
AT91C_BASE_WDTC->WDTC_WDCR = 1 | 0xA5000000; | ||
if (!HEARTBEAT) | ||
AT91C_BASE_WDTC->WDTC_WDCR = 1 | 0xA5000000; | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. The watchdog timer should be reset automatically before entering There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. it's continuously checked in timer0_vel_calc(), right? There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. After the power on, If watchdog time is not cleared automatically on
That's not what I would like to say in the previous comment. There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. As we discussed, I'm gonna stop the motor from the power cycle via a I/O pin. According to the hardware team, a corresponded pin has not been decided yet. |
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if (err_chk++ % 20 == 0) | ||
{ | ||
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@@ -826,6 +827,7 @@ int main() | |
if (DBGU_IsRxReady()) | ||
{ | ||
buf[nbuf] = DBGU_GetChar(); | ||
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if (buf[nbuf] == '\n' || buf[nbuf] == '\r') | ||
{ | ||
buf[nbuf] = 0; | ||
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@@ -860,6 +862,12 @@ int main() | |
USART_WriteBuffer(AT91C_BASE_US0, &buf[1], nbuf - 1); | ||
} | ||
break; | ||
case 't': | ||
{ | ||
if (HEARTBEAT) | ||
AT91C_BASE_WDTC->WDTC_WDCR = 1 | 0xA5000000; | ||
} | ||
break; | ||
} | ||
nbuf = 0; | ||
} | ||
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In my understanding, watchdog count clock is 32.768kHz divided by 128 = 256 Hz. (datasheet
15. Watchdog Timer (WDT)
)0x7d0 means 7.8 seconds?
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that's my bad. will revert it back.