bump fork for version 0.41 #20
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Mostly memory_libmap arg checks; puts the checks into an else block on the `if (help_mode)` check to avoid cases like `synth_ice40` listing `-no-auto-huge [-no-auto-huge]`. Also fix `map_iopad` section being empty in `synth_fabulous`.
…st (this documents the current behavior, not sure if it is desired functionality)
Add new verific testing environment CI
add support for using ABCs library merging when providing multiple liberty files
Previously `extract` on a `SigSpec` would always unpack it. Since a significant amount of `SigSpec`s have one or few chunks, it's worth having a dedicated implementation. This is especially true, since the RTLIL frontend calls into this for every `wire [lhs:rhs]` slice, making this `extract` take up 40% when profiling `read_rtlil` with one of the largest coarse grained RTLIL designs I had on hand. With this change the `read_rtlil` profile looks like I would expect it to look like, but I noticed that a lot of the other core RTLIL methods also are a bit too eager with unpacking or implementing `SigChunk`/`Const` overloads that just convert to a single chunk `SigSpec` and forward to the implementation for that, when a direct implementation would avoid temporary std::vector allocations. While not relevant for `read_rtlil`, to me it looks like there might be a few easy overall performance gains to be had by addressing this more generally.
rtlil: Add packed `extract` implementation for `SigSpec`
Typo fixing
fix hierarchy -generate mode handling of cells
* Also makes all ascii parsing finish reading lines and adds a small test
read_aiger: Fix incorrect read of binary Aiger without outputs
techmap: add dynamic cell type test
Test Case
```
module packed_dimensions_range_ordering (
input wire [0:4-1] in,
output wire [4-1:0] out
);
assign out = in;
endmodule : packed_dimensions_range_ordering
module instanciates_packed_dimensions_range_ordering (
input wire [4-1:0] in,
output wire [4-1:0] out
);
packed_dimensions_range_ordering U0 (
.in (in),
.out(out)
);
endmodule : instanciates_packed_dimensions_range_ordering
```
```
// with verific, does not pass formal
module instanciates_packed_dimensions_range_ordering(in, out);
input [3:0] in;
wire [3:0] in;
output [3:0] out;
wire [3:0] out;
assign out = { in[0], in[1], in[2], in[3] };
endmodule
// with surelog, passes formal
module instanciates_packed_dimensions_range_ordering(in, out);
input [3:0] in;
wire [3:0] in;
output [3:0] out;
wire [3:0] out;
assign out = in;
endmodule
```
Signed-off-by: Ethan Mahintorabi <[email protected]>
Signed-off-by: Ethan Mahintorabi <[email protected]>
In C and C++, a `\x` escape sequence consumes as many hexadecimal digits as there are available, so it is not composable with arbitrary alnum characters afterwards. An octal escape sequence like `\000` always has fixed width, avoiding an issue where `\x01c` and `\x1c` produce the same string.
Before this commit, the creation of (constant) attribute maps caused `debug_info()` (which is built with `__attribute__((optnone))`) to consume large amounts of stack space; up to tens of megabytes. This caused problems particularly on macOS, where the default stack size is 512 KiB. After this commit, `std::map` objects are no longer created inline in the `debug_info()` function, but are compiled to and then expanded from a string literal in a subroutine call. This reduces stack space usage by about 50%.
Before this commit, this function would create a temporary `std::string` per debug item (and scope). After this commit, an additional overload is used to push that down the call stack. This reduces stack usage by about 50% more on top of the previous commit.
This commit uses parameter packs to sink `debug_item()` construction into the `debug_info()`-specific `add()` overload. This makes the stack space use sub-linear in typical case rather than linear (which is still the worst case). Oddly, the stack slots that get allocated now are all for the `0` literal for `lsb_offset`. This could be fixed by allocating numbers statically but the existing reduction in stack use of ~98% for a representative example (Minerva SoC) should be enough.
cxxrtl: reduce stack space used by the `debug_info()` function
Add PR template
Add YosysHQ/abc as a submodule located in abc.
Make sure that we correctly adjust the value to align it to a zero indexed list with lsb = 0 Signed-off-by: Ethan Mahintorabi <[email protected]>
Currently only vs.yml and wasi.yml since emscripten is on the chopping block. Use fkirc/skip-duplicate-actions to skip duplicate action runs.
Reduce action spam when a PR source branch is on YosysHQ/yosys
Modify abc directory content check
frontend: Fixes verific import around range order
eder-matheus
merged commit a883985
into
The-OpenROAD-Project:master
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