Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

bump fork for version 0.46 #25

Merged
merged 249 commits into from
Oct 9, 2024
Merged

Conversation

eder-matheus
Copy link
Collaborator

No description provided.

povik and others added 30 commits July 18, 2024 13:08
This adds a generic non-recursive implementation of Tarjan's linear time
SCC algorithm that produces components in topological order. It can be
instantiated to work directly on any graph representation for which the
enumerate_nodes and enumerate_successors interface can be implemented.
When implementing custom log_... functions or custom overloads for the
core log functions like log_signal it is necessary to return `char *`
that are valid long enough.

The log_... functions implemented in log.cc use either `log_id_cache` or
`string_buf` which both are cleared on log_pop.

This commit adds a public `log_str` function which stores its argument
in the `log_id_cache` and returns the stored copy, such that custom
log functions outside of log.cc can also create strings that remain
valid until the next `log_pop`.
This is already supported by `SigSpec` and since both `SigChunk` and
`SigSpec` implement `extract` which is the multi-bit variant of this,
there is no good reason for `SigChunk` to not support
`SigBit operator[](int offset)`.
It adds `DriveBit`, `DriveChunk` and `DriveSpec` types which are similar
to `SigBit`, `SigChunk` and `SigSpec` but can also directly represent
cell ports, undriven bits and multiple drivers. For indexing an RTLIL
module and for querying signal drivers it comes with a `DriverMap` type
which is somewhat similar to a `SigMap` but is guaranteed to produce
signal drivers as returned representatives.

A `DriverMap` can also optionally preserve connections via intermediate
wires (e.g. querying the driver of a cell input port will return a
connected intermediate wire, querying the driver of that wire will
return the cell output port that's driving the wire).
donn and others added 29 commits October 7, 2024 16:39
* wheel versions now replace `+` with `.post` to match spec at https://packaging.python.org/en/latest/specifications/version-specifiers/
* CI updates:
  * Bump action versions
  * Disabled Windows for now and documented why
  * Added a new job to upload all wheels
  * Added new variable, `PYPI_INDEX`: fallback 'https://pypi.org/' if unset
  * Added new secret, `PYPI_TOKEN`
* .editorconfig now uses 2 spaces for YML (it kept setting mine to tabs
  and GitHub Actions doesn't like that)
quicklogic: Avoid carry chains in division mapping
read_liberty: Optionally import unit delay arcs
log: Never silence `log_cmd_error`
Since `docs/prep` is a prerequisite of `docs`, and should be the *only* prerequisite, calling `make docs` could end up hiding a problem with files missing from the uploaded artifact. Instead, call `make` from the docs directory which should be closer to what will run on RTDs.
Remove make docs race conditions (and other docs fixes)
Explictly #include <variant> for std::variant usage.
Fix CI by adding lld as brew package
CI: force brew formula update
This caused compilation to fail when the argument of any, not just
UNICHAR formatting operations, is bigger than 32 bits.

Fixes #4644
@eder-matheus eder-matheus merged commit e5713bc into The-OpenROAD-Project:master Oct 9, 2024
6 checks passed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.