[HACK] Import temporary files for the power switch

Signed-off-by: Sylvain Munaut <[email protected]>

pg/tt_pg_vdd_1.lef

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+VERSION 5.7 ;
+  NOWIREEXTENSIONATPIN ON ;
+  DIVIDERCHAR "/" ;
+  BUSBITCHARS "[]" ;
+MACRO tt_pg_vdd_1
+  CLASS BLOCK ;
+  FOREIGN tt_pg_vdd_1 ;
+  ORIGIN 0.000 0.000 ;
+  SIZE 9.200 BY 111.520 ;
+  PIN VGND
+    DIRECTION INPUT ;
+    USE GROUND ;
+    PORT
+      LAYER met4 ;
+        RECT 0.000 0.000 1.200 110.000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 8.000 0.000 9.200 110.000 ;
+    END
+  END VGND
+  PIN VPWR
+    DIRECTION INPUT ;
+    USE POWER ;
+    PORT
+      LAYER met4 ;
+        RECT 1.700 0.000 4.350 110.000 ;
+    END
+  END VPWR
+  PIN GPWR
+    DIRECTION OUTPUT ;
+    USE POWER ;
+    PORT
+      LAYER met4 ;
+        RECT 4.850 0.000 7.500 110.000 ;
+    END
+  END GPWR
+  PIN ctrl
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 0.000 111.020 9.200 111.520 ;
+    END
+  END ctrl
+END tt_pg_vdd_1
+END LIBRARY
+

pg/tt_pg_vdd_1.mag

@@ -0,0 +1,21 @@
+magic
+tech sky130A
+timestamp 1697029486
+<< metal4 >>
+rect 0 11102 920 11152
+rect 0 0 120 11000
+rect 170 0 435 11000
+rect 485 0 750 11000
+rect 800 0 920 11000
+<< labels >>
+rlabel metal4 0 0 120 11000 1 VGND
+port 1 n ground input
+rlabel metal4 800 0 920 11000 1 VGND
+port 1 n ground input
+rlabel metal4 170 0 435 11000 1 VPWR
+port 2 n power input
+rlabel metal4 485 0 750 11000 1 GPWR
+port 3 n power output
+rlabel metal4 0 11102 920 11152 1 ctrl
+port 4 n signal input
+<< end >>

pg/tt_pg_vdd_1.tcl

@@ -0,0 +1,44 @@
+cellname rename (UNNAMED) tt_pg_vdd_1
+
+box position 0 0
+box heigh 11000
+box width 120
+paint met4
+label VGND
+port make
+port class input
+port use ground
+
+box position 800 0
+paint met4
+label VGND
+port make
+port class input
+port use ground
+
+box width 265
+box position 170 0
+paint met4
+label VPWR
+port make
+port class input
+port use power 
+
+box position 485 0
+paint met4
+label GPWR
+port make
+port class output
+port use power 
+
+box height 50
+box width 920
+box position 0 11102
+paint met4
+label ctrl
+port make
+port class input
+port use signal
+
+lef write /tmp/tt_pg_vdd_1.lef
+gds write /tmp/tt_pg_vdd_1.gds

pg/tt_pg_vdd_1.v

@@ -0,0 +1,20 @@
+/*
+ * tt_pg_vdd_1.v
+ *
+ * Blackbox for the VDD power switches
+ *
+ * Copyright (c) 2023 Sylvain Munaut <[email protected]>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+(* blackbox *)
+module tt_pg_vdd_1 (
+`ifdef USE_POWER_PINS
+	input  wire VGND,
+	input  wire VPWR,
+	output wire GPWR,
+`endif
+	input  wire ctrl
+);
+
+endmodule

pg/tt_pg_vdd_2.lef

@@ -0,0 +1,48 @@
+VERSION 5.7 ;
+  NOWIREEXTENSIONATPIN ON ;
+  DIVIDERCHAR "/" ;
+  BUSBITCHARS "[]" ;
+MACRO tt_pg_vdd_2
+  CLASS BLOCK ;
+  FOREIGN tt_pg_vdd_2 ;
+  ORIGIN 0.000 0.000 ;
+  SIZE 9.200 BY 225.760 ;
+  PIN VGND
+    DIRECTION INPUT ;
+    USE GROUND ;
+    PORT
+      LAYER met4 ;
+        RECT 0.000 0.000 1.200 224.240 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 8.000 0.000 9.200 224.240 ;
+    END
+  END VGND
+  PIN VPWR
+    DIRECTION INPUT ;
+    USE POWER ;
+    PORT
+      LAYER met4 ;
+        RECT 1.700 0.000 4.350 224.240 ;
+    END
+  END VPWR
+  PIN GPWR
+    DIRECTION OUTPUT ;
+    USE POWER ;
+    PORT
+      LAYER met4 ;
+        RECT 4.850 0.000 7.500 224.240 ;
+    END
+  END GPWR
+  PIN ctrl
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 0.000 225.260 9.200 225.760 ;
+    END
+  END ctrl
+END tt_pg_vdd_2
+END LIBRARY
+

pg/tt_pg_vdd_2.mag

@@ -0,0 +1,21 @@
+magic
+tech sky130A
+timestamp 1697051837
+<< metal4 >>
+rect 0 22526 920 22576
+rect 0 0 120 22424
+rect 170 0 435 22424
+rect 485 0 750 22424
+rect 800 0 920 22424
+<< labels >>
+rlabel metal4 0 0 120 22424 1 VGND
+port 1 n ground input
+rlabel metal4 800 0 920 22424 1 VGND
+port 1 n ground input
+rlabel metal4 170 0 435 22424 1 VPWR
+port 2 n power input
+rlabel metal4 485 0 750 22424 1 GPWR
+port 3 n power output
+rlabel metal4 0 22526 920 22576 1 ctrl
+port 4 n signal input
+<< end >>

pg/tt_pg_vdd_2.tcl

@@ -0,0 +1,45 @@
+cellname rename (UNNAMED) tt_pg_vdd_2
+
+box position 0 0
+box heigh 22424
+box width 120
+paint met4
+label VGND
+port make
+port class input
+port use ground
+
+box position 800 0
+paint met4
+label VGND
+port make
+port class input
+port use ground
+
+box width 265
+box position 170 0
+paint met4
+label VPWR
+port make
+port class input
+port use power 
+
+box position 485 0
+paint met4
+label GPWR
+port make
+port class output
+port use power 
+
+box height 50
+box width 920
+box position 0 22526
+paint met4
+label ctrl
+port make
+port class input
+port use signal
+
+lef write /tmp/tt_pg_vdd_2.lef
+gds write /tmp/tt_pg_vdd_2.gds
+save tt_pg_vdd_2.mag

pg/tt_pg_vdd_2.v

@@ -0,0 +1,20 @@
+/*
+ * tt_pg_vdd_2.v
+ *
+ * Blackbox for the VDD power switches
+ *
+ * Copyright (c) 2023 Sylvain Munaut <[email protected]>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+(* blackbox *)
+module tt_pg_vdd_2 (
+`ifdef USE_POWER_PINS
+	input  wire VGND,
+	input  wire VPWR,
+	output wire GPWR,
+`endif
+	input  wire ctrl
+);
+
+endmodule