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update from verilog template #3

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update from verilog template #3

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66c22d9
fix: restrict decap/fill cells to solve poly density issue
urish Nov 6, 2024
26e4dc9
fix: use DECAP_CELL / FILL_CELL settings from PDK
urish Nov 6, 2024
99c75c9
docs: mention Surfer as an alternative to GTKWave (#13)
tommythorn Nov 10, 2024
c71513c
docs: outdated template notice
urish Nov 13, 2024
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4 changes: 4 additions & 0 deletions README.md
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Original file line number Diff line number Diff line change
@@ -1,5 +1,9 @@
![](../../workflows/gds/badge.svg) ![](../../workflows/docs/badge.svg) ![](../../workflows/test/badge.svg) ![](../../workflows/fpga/badge.svg)

# ⚠️ This template is old and outdated ⚠️

Please use **[tt10-verilog-template](https://github.com/TinyTapeout/tt10-verilog-template)** for new projects.

# Tiny Tapeout Verilog Project Template

- [Read the documentation for project](docs/info.md)
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9 changes: 0 additions & 9 deletions src/config.json
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Expand Up @@ -60,15 +60,6 @@

"FP_PDN_VPITCH": 38.87,

"//": "Use alternative efabless decap cells to solve LI density issue",
"DECAP_CELL": [
"sky130_fd_sc_hd__decap_3",
"sky130_fd_sc_hd__decap_4",
"sky130_fd_sc_hd__decap_6",
"sky130_fd_sc_hd__decap_8",
"sky130_ef_sc_hd__decap_12"
],

"//": "Clock",
"RUN_CTS": 1,

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6 changes: 6 additions & 0 deletions test/README.md
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Expand Up @@ -26,6 +26,12 @@ make -B GATES=yes

## How to view the VCD file

Using GTKWave
```sh
gtkwave tb.vcd tb.gtkw
```

Using Surfer
```sh
surfer tb.vcd
```
2 changes: 1 addition & 1 deletion test/tb.v
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Expand Up @@ -6,7 +6,7 @@
*/
module tb ();

// Dump the signals to a VCD file. You can view it with gtkwave.
// Dump the signals to a VCD file. You can view it with gtkwave or surfer.
initial begin
$dumpfile("tb.vcd");
$dumpvars(0, tb);
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