WIP FP context switching

documentation/manual/ports.tex

@@ -979,7 +979,7 @@ \subsection{Dispatching the service call}
 
 \subsubsection{Preparing the environment}
 
-When the Supervisor Call begins execution, the kernel stack has the mapping depicted in figure \ref{fig:CM4StackAfterInvoque}.
+When the Supervisor Call begins execution, the process stack has the mapping depicted in figure \ref{fig:CM4StackAfterInvoque}.
 
 \begin{figure}[htbp] %  figure placement: here, top, bottom, or page
 \begin{minipage}{0.5\textwidth}
@@ -1210,7 +1210,41 @@ \subsubsection{Getting back to the process}
   bx lr
 \end{lstlisting}
 
-=====================================================================
+\subsection{Cortex-M FPU support}
+
+Processors with a floating-point unit add the following registers to the context:
+\begin{itemize}
+\item 32 32-bit registers named \reg{s0} to \reg{s31} which can be seen as 16 64-bit registers named \reg{d0} to \reg{d15} for instructions operating on double-precision floating-point numbers.
+\item \reg{fpscr} is the floating-point status and control register.
+\item \reg{fpexc} is the floating-point exception register.
+\end{itemize}
+
+\reg{fpsid} is the floating-point system ID register but as this register seems to be read-only, it is not part of the context.
+
+When floating point is activated, the static task descriptor has an additional member, a pointer to the floating point context structure, which is located just after the pointer to the integer context structure. Function that save and load the contexte, \cfunction{tpl_save_context}, \cfunction{tpl_load_context}, \cfunction{tpl_save_context_under_it} and \cfunction{tpl_load_context_under_it} all have a pointer to the static task descriptor in \reg{r0} register. The floating context is accessed by reading its pointer:
+
+\begin{lstlisting}[language=C]
+  ldr r1,[r0,#FLOAT_CONTEXT]
+\end{lstlisting}
+
+Saving the floating-point context is a two-part process. First, the registers \reg{s0} to \reg{s31} are saved.
+
+\warning{C'est pas clair. Les registres doivent être consécutifs mais je ne sais pas combien de registres on peut écrire d'un coup. Mais ça pourrait ressembler à ça.}
+
+\begin{lstlisting}[language=C]
+  vstm r1!,{s0-s31}
+\end{lstlisting}
+
+Then:
+
+\begin{lstlisting}[language=C]
+  mrs r2,fpscr
+  str r2,[r1]
+  mrs r2,fpexc
+  str r2,[r1,#4]
+\end{lstlisting}
+
+
 
 \subsection{Interrupt handler}
 

goil/templates/config/cortex-m/armv7em/stm32h743/config.oil

@@ -1230,11 +1230,10 @@ CPU stm32h743 {
 
   PLATFORM_FILES stm32h743 {
     PATH = "cortex-m/armv7em/stm32h743";
-    CFILE = "handlers_stm32l432.c";
-    CFILE = "startup_stm32l432.c";
-    CFILE = "system_stm32l4xx.c";
+    CFILE = "handlers_stm32h743.c";
+    CFILE = "startup_stm32h743zitx.c";
+    CFILE = "system_stm32h743.c";
     CFILE = "tpl_machine_stm32h743.c";
-    CFILE = "tpl_memory_protection.c";
   };
 
   PLATFORM_FILES stm32h743_trace {

machines/cortex-m/armv7em/tpl_ctx_switch.S

@@ -81,18 +81,7 @@
  *----------------------------------------------------------------------------*
  */
 
-#define CTX_GPR4    0
-#define CTX_GPR5    4
-#define CTX_GPR6    8
-#define CTX_GPR7    12
-#define CTX_GPR8    16
-#define CTX_GPR9    20
-#define CTX_GPR10   24
-#define CTX_GPR11   28
-#define CTX_PSP     32
-
-#define INT_CONTEXT   0
-#define FLOAT_CONTEXT 4
+#include "tpl_regs_offsets.h"
 
 /*=============================================================================
  * tpl_save_context is used to save the context of the running task.
@@ -143,6 +132,9 @@ tpl_save_context:
     mrs r2,psp
     str r2,[r1,#CTX_PSP]
 
+#if WITH_FLOAT == YES
+#endif
+
     bx  lr
 
 /*=============================================================================
@@ -194,6 +186,9 @@ tpl_load_context:
     ldr r2,[r1,#CTX_PSP]
     msr psp,r2
 
+#if WITH_FLOAT == YES
+#endif
+
     bx   lr
 
 #define OS_STOP_SEC_CODE

machines/cortex-m/armv7em/tpl_ctx_switch_under_it.S

@@ -81,18 +81,7 @@
  *----------------------------------------------------------------------------*
  */
 
-#define CTX_GPR4    0
-#define CTX_GPR5    4
-#define CTX_GPR6    8
-#define CTX_GPR7    12
-#define CTX_GPR8    16
-#define CTX_GPR9    20
-#define CTX_GPR10   24
-#define CTX_GPR11   28
-#define CTX_PSP     32
-
-#define INT_CONTEXT   0
-#define FLOAT_CONTEXT 4
+#include "tpl_regs_offsets.h"
 
 /*=============================================================================
  * tpl_save_context_under_it is used to save the context of the running task.
@@ -130,6 +119,9 @@ tpl_save_context_under_it:
     mrs r2,psp
     str r2,[r1,#CTX_PSP]
 
+#if WITH_FLOAT == YES
+#endif
+
     bx  lr
 
 /*=============================================================================
@@ -170,6 +162,9 @@ tpl_load_context_under_it:
     ldr r2,[r1,#CTX_PSP]
     msr psp,r2
 
+#if WITH_FLOAT == YES
+#endif
+
     bx  lr
 
 #define OS_STOP_SEC_CODE

machines/cortex-m/armv7em/tpl_regs_offsets.h

@@ -0,0 +1,52 @@
+#ifndef __TPL_REGS_OFFSETS_H__
+#define __TPL_REGS_OFFSETS_H__
+
+#define CTX_GPR4 0
+#define CTX_GPR5 4
+#define CTX_GPR6 8
+#define CTX_GPR7 12
+#define CTX_GPR8 16
+#define CTX_GPR9 20
+#define CTX_GPR10 24
+#define CTX_GPR11 28
+#define CTX_PSP 32
+
+#define F_CTX_S0 0
+#define F_CTX_S1 4
+#define F_CTX_S2 8
+#define F_CTX_S3 12
+#define F_CTX_S4 16
+#define F_CTX_S5 20
+#define F_CTX_S6 24
+#define F_CTX_S7 28
+#define F_CTX_S8 32
+#define F_CTX_S9 36
+#define F_CTX_S10 40
+#define F_CTX_S11 44
+#define F_CTX_S12 48
+#define F_CTX_S13 52
+#define F_CTX_S14 56
+#define F_CTX_S15 60
+#define F_CTX_S16 64
+#define F_CTX_S17 68
+#define F_CTX_S18 72
+#define F_CTX_S19 76
+#define F_CTX_S20 80
+#define F_CTX_S21 84
+#define F_CTX_S22 88
+#define F_CTX_S23 92
+#define F_CTX_S24 96
+#define F_CTX_S25 100
+#define F_CTX_S26 104
+#define F_CTX_S27 108
+#define F_CTX_S28 112
+#define F_CTX_S29 116
+#define F_CTX_S30 120
+#define F_CTX_S31 124
+#define F_CTX_FPSCR 128
+#define F_CTX_FPEXC 132
+
+#define INT_CONTEXT 0
+#define FLOAT_CONTEXT 4
+
+#endif

machines/cortex-m/tpl_machine.h

@@ -20,13 +20,15 @@
  * $Date: 2010-10-27 15:34:11 +0200 (mer., 27 oct. 2010) $
  * $Rev: 1227 $
  * $Author: pacco $
- * $URL: https://trampoline.rts-software.org/svn/trunk/machines/thumb2/cortex-m3/tpl_machine.h $
+ * $URL:
+ * https://trampoline.rts-software.org/svn/trunk/machines/thumb2/cortex-m3/tpl_machine.h
+ * $
  */
 #ifndef TPL_MACHINE_H
 #define TPL_MACHINE_H
 
-#include "tpl_machine_cortex.h"
 #include "cmsis_wrapper.h"
+#include "tpl_machine_cortex.h"
 
 /**
  * Gives the ARM processor mode the normal user tasks
@@ -41,17 +43,17 @@
  *
  * The size of the stack of the idle task
  */
-#define IDLE_STACK_SIZE  300
+#define IDLE_STACK_SIZE 300
 
-struct TPL_CONTEXT {
-	arm_core_context	*cc;
-#ifdef WITH_FLOAT
-  arm_float_context	*fc;
+struct TPL_CONTEXT
+{
+  arm_core_context *cc;
+#if WITH_FLOAT == YES
+  arm_float_context *fc;
 #endif
 };
 
-
-//typedef struct TPL_CONTEXT tpl_context;
+// typedef struct TPL_CONTEXT tpl_context;
 
 typedef struct ARM_CORE_CONTEXT *tpl_context;
 
@@ -60,8 +62,8 @@ extern struct ARM_CORE_CONTEXT idle_task_context;
 extern unsigned long _estack;
 
 /*
- * Configuration of systick timer (can be a generic timer if systick is not available
- * on the target) for alarms and schedule tables.
+ * Configuration of systick timer (can be a generic timer if systick is not
+ * available on the target) for alarms and schedule tables.
  */
 FUNC(void, OS_CODE) tpl_set_systick_timer();
 

machines/cortex-m/tpl_machine_cortex.h

@@ -26,24 +26,24 @@
 #ifndef TPL_MACHINE_CORTEX_H
 #define TPL_MACHINE_CORTEX_H
 
-#include "tpl_os_std_types.h"
-#include "tpl_os_internal_types.h"
-#include "tpl_os_custom_types.h"
 #include "tpl_machine.h"
+#include "tpl_os_custom_types.h"
+#include "tpl_os_internal_types.h"
 #include "tpl_os_kernel_stack.h"
+#include "tpl_os_std_types.h"
 
 /**
  * Definition of kernel access defines.
  * Specific to the target.
  */
 
-#define TPL_KERN_OFFSET_S_RUNNING     (0)
-#define TPL_KERN_OFFSET_S_ELECTED     (4)
-#define TPL_KERN_OFFSET_RUNNING       (8)
-#define TPL_KERN_OFFSET_ELECTED       (12)
-#define TPL_KERN_OFFSET_RUNNING_ID    (16)
-#define TPL_KERN_OFFSET_ELECTED_ID    (20)
-#define TPL_KERN_OFFSET_NEED_SWITCH   (24)
+#define TPL_KERN_OFFSET_S_RUNNING (0)
+#define TPL_KERN_OFFSET_S_ELECTED (4)
+#define TPL_KERN_OFFSET_RUNNING (8)
+#define TPL_KERN_OFFSET_ELECTED (12)
+#define TPL_KERN_OFFSET_RUNNING_ID (16)
+#define TPL_KERN_OFFSET_ELECTED_ID (20)
+#define TPL_KERN_OFFSET_NEED_SWITCH (24)
 #define TPL_KERN_OFFSET_NEED_SCHEDULE (25)
 
 /**
@@ -72,12 +72,17 @@
 #define ARM_CORE_EXCEPTION_FRAME_SIZE ((uint32)32)
 /* ARM_INITIAL_EXC_RETURN
  * Default value of exception return value
- * 0xFFFFFFF1 - Return to Handler mode, exception return uses non-floating-point state from the MSP and execution uses MSP after return.
- * 0xFFFFFFF9 - Return to Thread mode, exception return uses non-floating-point state from MSP and execution uses MSP after return.
- * 0xFFFFFFFD - Return to Thread mode, exception return uses non-floating-point state from the PSP and execution uses PSP after return.
- * 0xFFFFFFE1 - Return to Handler mode, exception return uses floating-point-state from MSP and execution uses MSP after return.
- * 0xFFFFFFE9 - Return to Thread mode, exception return uses floating-point state from MSP and execution uses MSP after return.
- * 0xFFFFFFED - Return to Thread mode, exception return uses floating-point state from PSP and execution uses PSP after return.
+ * 0xFFFFFFF1 - Return to Handler mode, exception return uses non-floating-point
+ * state from the MSP and execution uses MSP after return. 0xFFFFFFF9 - Return
+ * to Thread mode, exception return uses non-floating-point state from MSP and
+ * execution uses MSP after return. 0xFFFFFFFD - Return to Thread mode,
+ * exception return uses non-floating-point state from the PSP and execution
+ * uses PSP after return. 0xFFFFFFE1 - Return to Handler mode, exception return
+ * uses floating-point-state from MSP and execution uses MSP after return.
+ * 0xFFFFFFE9 - Return to Thread mode, exception return uses floating-point
+ * state from MSP and execution uses MSP after return. 0xFFFFFFED - Return to
+ * Thread mode, exception return uses floating-point state from PSP and
+ * execution uses PSP after return.
  */
 #define ARM_INITIAL_EXC_RETURN ((uint32)0xFFFFFFF9)
 
@@ -109,29 +114,30 @@
 
 typedef struct ARM_CORE_CONTEXT
 {
-  uint32 gpr4;          /* General purpose register r4 */
-  uint32 gpr5;          /* General purpose register r5 */
-  uint32 gpr6;          /* General purpose register r6 */
-  uint32 gpr7;          /* General purpose register r7 */
-  uint32 gpr8;          /* General purpose register r8 */
-  uint32 gpr9;          /* General purpose register r9 */
-  uint32 gpr10;         /* General purpose register r10 */
-  uint32 gpr11;         /* General purpose register r11 */
-	uint32 stackPointer;  /* Stack Pointer - r13          */
+  uint32 gpr4;         /* General purpose register r4 */
+  uint32 gpr5;         /* General purpose register r5 */
+  uint32 gpr6;         /* General purpose register r6 */
+  uint32 gpr7;         /* General purpose register r7 */
+  uint32 gpr8;         /* General purpose register r8 */
+  uint32 gpr9;         /* General purpose register r9 */
+  uint32 gpr10;        /* General purpose register r10 */
+  uint32 gpr11;        /* General purpose register r11 */
+  uint32 stackPointer; /* Stack Pointer - r13          */
 } arm_core_context;
 
-#ifdef WITH_FLOAT
+#if WITH_FLOAT == YES
 /*
  * Floating Point Context
  */
-struct ARM_FLOAT_CONTEXT {
-	/* is Single Precision Register s0-s31 */
-    double  spr[32];
-	/* Floating Point Status and Control Register */
-    double  fpscr;
-};
-
-typedef struct ARM_FLOAT_CONTEXT arm_float_context;
+typedef struct ARM_FLOAT_CONTEXT
+{
+  /* is Single Precision Register s0-s31 */
+  float spr[32];
+  /* Floating Point Status and Control Register */
+  uint32 fpscr;
+  /* Floating-point exception register */
+  uint32 fpexc;
+} arm_float_context;
 #endif
 
 /**
@@ -147,9 +153,10 @@ typedef uint32 tpl_stack_size;
 /**
  * Stack definition
  */
-struct TPL_STACK {
-    tpl_stack_word  *stack_zone;
-    tpl_stack_size  stack_size;
+struct TPL_STACK
+{
+  tpl_stack_word *stack_zone;
+  tpl_stack_size stack_size;
 };
 
 /**
@@ -164,15 +171,15 @@ typedef struct TPL_STACK tpl_stack;
  */
 #define IDLE_ENTRY tpl_sleep
 
-#define DISABLE_FIQ() __asm__ __volatile__ ("cpsid f;")
+#define DISABLE_FIQ() __asm__ __volatile__("cpsid f;")
 
-#define ENABLE_FIQ()  __asm__ __volatile__ ("cpsie f;")
+#define ENABLE_FIQ() __asm__ __volatile__("cpsie f;")
 
-#define DISABLE_IRQ() __asm__ __volatile__ ("cpsid i;")
+#define DISABLE_IRQ() __asm__ __volatile__("cpsid i;")
 
-#define ENABLE_IRQ()  __asm__ __volatile__ ("cpsie i;")
+#define ENABLE_IRQ() __asm__ __volatile__("cpsie i;")
 
-FUNC (void, OS_CODE) tpl_init_machine_specific (void);
+FUNC(void, OS_CODE) tpl_init_machine_specific(void);
 
 #endif /* TPL_MACHINE_CORTEX_H */