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@wrongnull
wrongnull committed Jul 25, 2024
2 parents d9fb650 + 0ba90c7 commit d1c058c
Showing 1 changed file with 3 additions and 51 deletions.
54 changes: 3 additions & 51 deletions src/aro/target.zig
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Original file line number Diff line number Diff line change
Expand Up @@ -17,8 +17,6 @@ pub fn intMaxType(target: std.Target) Type {
.riscv64,
.powerpc64,
.powerpc64le,
.tce,
.tcele,
.ve,
=> return .{ .specifier = .long },

Expand All @@ -37,11 +35,7 @@ pub fn intMaxType(target: std.Target) Type {

/// intptr_t for this target
pub fn intPtrType(target: std.Target) Type {
switch (target.os.tag) {
.haiku => return .{ .specifier = .long },
.nacl => return .{ .specifier = .int },
else => {},
}
if (target.os.tag == .haiku) return .{ .specifier = .long };

switch (target.cpu.arch) {
.aarch64, .aarch64_be => switch (target.os.tag) {
Expand All @@ -55,8 +49,6 @@ pub fn intPtrType(target: std.Target) Type {
.riscv32,
.xcore,
.hexagon,
.tce,
.tcele,
.m68k,
.spir,
.spirv32,
Expand Down Expand Up @@ -162,7 +154,7 @@ pub fn isTlsSupported(target: std.Target) bool {
return supported;
}
return switch (target.cpu.arch) {
.tce, .tcele, .bpfel, .bpfeb, .msp430, .nvptx, .nvptx64, .x86, .arm, .armeb, .thumb, .thumbeb => false,
.bpfel, .bpfeb, .msp430, .nvptx, .nvptx64, .x86, .arm, .armeb, .thumb, .thumbeb => false,
else => true,
};
}
Expand Down Expand Up @@ -475,30 +467,22 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
.csky,
.hexagon,
.m68k,
.le32,
.mips,
.mipsel,
.powerpc,
.powerpcle,
.r600,
.riscv32,
.sparc,
.sparcel,
.tce,
.tcele,
.thumb,
.thumbeb,
.x86,
.xcore,
.nvptx,
.amdil,
.hsail,
.spir,
.kalimba,
.shave,
.lanai,
.wasm32,
.renderscript32,
.aarch64_32,
.spirv,
.spirv32,
Expand All @@ -509,14 +493,10 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {

.aarch64 => copy.cpu.arch = .arm,
.aarch64_be => copy.cpu.arch = .armeb,
.le64 => copy.cpu.arch = .le32,
.amdil64 => copy.cpu.arch = .amdil,
.nvptx64 => copy.cpu.arch = .nvptx,
.wasm64 => copy.cpu.arch = .wasm32,
.hsail64 => copy.cpu.arch = .hsail,
.spir64 => copy.cpu.arch = .spir,
.spirv64 => copy.cpu.arch = .spirv32,
.renderscript64 => copy.cpu.arch = .renderscript32,
.loongarch64 => copy.cpu.arch = .loongarch32,
.mips64 => copy.cpu.arch = .mips,
.mips64el => copy.cpu.arch = .mipsel,
Expand All @@ -541,12 +521,8 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
.lanai,
.m68k,
.msp430,
.r600,
.shave,
.sparcel,
.spu_2,
.tce,
.tcele,
.xcore,
.xtensa,
=> return null,
Expand All @@ -556,14 +532,10 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
.amdgcn,
.bpfeb,
.bpfel,
.le64,
.amdil64,
.nvptx64,
.wasm64,
.hsail64,
.spir64,
.spirv64,
.renderscript64,
.loongarch64,
.mips64,
.mips64el,
Expand All @@ -577,18 +549,14 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
=> {}, // Already 64 bit

.aarch64_32 => copy.cpu.arch = .aarch64,
.amdil => copy.cpu.arch = .amdil64,
.arm => copy.cpu.arch = .aarch64,
.armeb => copy.cpu.arch = .aarch64_be,
.hsail => copy.cpu.arch = .hsail64,
.le32 => copy.cpu.arch = .le64,
.loongarch32 => copy.cpu.arch = .loongarch64,
.mips => copy.cpu.arch = .mips64,
.mipsel => copy.cpu.arch = .mips64el,
.nvptx => copy.cpu.arch = .nvptx64,
.powerpc => copy.cpu.arch = .powerpc64,
.powerpcle => copy.cpu.arch = .powerpc64le,
.renderscript32 => copy.cpu.arch = .renderscript64,
.riscv32 => copy.cpu.arch = .riscv64,
.sparc => copy.cpu.arch = .sparc64,
.spir => copy.cpu.arch = .spir64,
Expand Down Expand Up @@ -635,16 +603,13 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
.powerpcle => "powerpcle",
.powerpc64 => "powerpc64",
.powerpc64le => "powerpc64le",
.r600 => "r600",
.amdgcn => "amdgcn",
.riscv32 => "riscv32",
.riscv64 => "riscv64",
.sparc => "sparc",
.sparc64 => "sparc64",
.sparcel => "sparcel",
.s390x => "s390x",
.tce => "tce",
.tcele => "tcele",
.thumb => "thumb",
.thumbeb => "thumbeb",
.x86 => "i386",
Expand All @@ -653,24 +618,15 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
.xtensa => "xtensa",
.nvptx => "nvptx",
.nvptx64 => "nvptx64",
.le32 => "le32",
.le64 => "le64",
.amdil => "amdil",
.amdil64 => "amdil64",
.hsail => "hsail",
.hsail64 => "hsail64",
.spir => "spir",
.spir64 => "spir64",
.spirv => "spirv",
.spirv32 => "spirv32",
.spirv64 => "spirv64",
.kalimba => "kalimba",
.shave => "shave",
.lanai => "lanai",
.wasm32 => "wasm32",
.wasm64 => "wasm64",
.renderscript32 => "renderscript32",
.renderscript64 => "renderscript64",
.ve => "ve",
// Note: spu_2 is not supported in LLVM; this is the Zig arch name
.spu_2 => "spu_2",
Expand All @@ -685,9 +641,8 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
.dragonfly => "dragonfly",
.freebsd => "freebsd",
.fuchsia => "fuchsia",
.kfreebsd => "kfreebsd",
.linux => "linux",
.lv2 => "lv2",
.ps3 => "lv2",
.netbsd => "netbsd",
.openbsd => "openbsd",
.solaris => "solaris",
Expand All @@ -697,7 +652,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
.haiku => "haiku",
.minix => "minix",
.rtems => "rtems",
.nacl => "nacl",
.aix => "aix",
.cuda => "cuda",
.nvcl => "nvcl",
Expand Down Expand Up @@ -749,7 +703,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
.gnueabi => "gnueabi",
.gnueabihf => "gnueabihf",
.gnuf32 => "gnuf32",
.gnuf64 => "gnuf64",
.gnusf => "gnusf",
.gnux32 => "gnux32",
.gnuilp32 => "gnuilp32",
Expand All @@ -764,7 +717,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
.msvc => "msvc",
.itanium => "itanium",
.cygnus => "cygnus",
.coreclr => "coreclr",
.simulator => "simulator",
.macabi => "macabi",
.pixel => "pixel",
Expand Down

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