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Add an ability to replay and loop FIFO data #24

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Add an ability to replay and loop FIFO data #24

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5b4e422
Add an ability to replay and loop FIFO data (created by Natt, just re…
visual-trials Nov 24, 2023
ac1c7f6
removed syn_hier attributes in psg.v and pcm.v
visual-trials Nov 24, 2023
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4 changes: 4 additions & 0 deletions fpga/source/audio/audio.v
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Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,8 @@ module audio(

// Audio FIFO interface
input wire fifo_reset,
input wire fifo_restart,
input wire fifo_loop,
input wire [7:0] fifo_wrdata,
input wire fifo_write,
output wire fifo_full,
Expand Down Expand Up @@ -70,6 +72,8 @@ module audio(

// Audio FIFO interface
.fifo_reset(fifo_reset),
.fifo_restart(fifo_restart),
.fifo_loop(fifo_loop),
.fifo_wrdata(fifo_wrdata),
.fifo_write(fifo_write),
.fifo_full(fifo_full),
Expand Down
7 changes: 6 additions & 1 deletion fpga/source/audio/audio_fifo.v
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Expand Up @@ -6,7 +6,8 @@ module audio_fifo(

input wire [7:0] wrdata,
input wire wr_en,

input wire rd_rst,

output reg [7:0] rddata,
input wire rd_en,

Expand Down Expand Up @@ -43,6 +44,10 @@ module audio_fifo(
rddata <= mem_r[rdidx_r];
rdidx_r <= rdidx_next;
end

if (rd_rst) begin
rdidx_r <= 0;
end
end
end

Expand Down
63 changes: 41 additions & 22 deletions fpga/source/audio/pcm.v
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Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,8 @@ module pcm(

// Audio FIFO interface
input wire fifo_reset,
input wire fifo_restart,
input wire fifo_loop,
input wire [7:0] fifo_wrdata,
input wire fifo_write,
output wire fifo_full,
Expand All @@ -22,7 +24,7 @@ module pcm(

// Audio output
output wire [15:0] left_audio,
output wire [15:0] right_audio) /* synthesis syn_hier = "hard" */;
output wire [15:0] right_audio);


//////////////////////////////////////////////////////////////////////////
Expand All @@ -42,6 +44,7 @@ module pcm(

.rddata(fifo_rddata),
.rd_en(fifo_read),
.rd_rst(fifo_restart_r),

.empty(fifo_empty),
.almost_empty(fifo_almost_empty),
Expand Down Expand Up @@ -82,6 +85,8 @@ module pcm(
FETCH_R_15_8 = 3'd4,
DONE = 3'd5;

reg fifo_restart_r, fifo_restart_next;
reg fifo_restart_l_r, fifo_restart_l_next;
reg [2:0] state_r, state_next;
reg [15:0] left_sample_r, left_sample_next;
reg [15:0] right_sample_r, right_sample_next;
Expand All @@ -93,25 +98,32 @@ module pcm(
wire [15:0] right_sample = mode_16bit ? right_sample_r : {right_sample_r[7:0], 8'b0};

always @* begin
state_next = state_r;
left_sample_next = left_sample_r;
right_sample_next = right_sample_r;
left_output_next = left_output_r;
right_output_next = right_output_r;
fifo_read = 0;

state_next = state_r;
left_sample_next = left_sample_r;
right_sample_next = right_sample_r;
left_output_next = left_output_r;
right_output_next = right_output_r;
fifo_read = 0;
fifo_restart_l_next = fifo_restart_l_r | fifo_restart;
fifo_restart_next = 0;

case (state_r)
IDLE: begin
if (fifo_empty) begin
left_output_next = 0;
right_output_next = 0;
if (fifo_restart_l_r) begin
fifo_restart_next = 1;
fifo_restart_l_next = 0;
end

if (new_sample && !fifo_empty) begin
left_sample_next = 0;
right_sample_next = 0;
state_next = FETCH_L_7_0;
fifo_read = 1;
if (new_sample) begin
if (fifo_empty) begin
left_output_next = 0;
right_output_next = 0;
end else begin
left_sample_next = 0;
right_sample_next = 0;
state_next = FETCH_L_7_0;
fifo_read = 1;
end
end
end

Expand Down Expand Up @@ -162,6 +174,9 @@ module pcm(
end
endcase

if (fifo_empty && fifo_loop) begin
fifo_restart_next = 1;
end
if (state_r != DONE && fifo_empty) begin
fifo_read = 0;
state_next = IDLE;
Expand All @@ -171,18 +186,22 @@ module pcm(

always @(posedge clk or posedge rst) begin
if (rst) begin
state_r <= IDLE;
left_sample_r <= 0;
right_sample_r <= 0;
left_output_r <= 0;
right_output_r <= 0;

state_r <= IDLE;
left_sample_r <= 0;
right_sample_r <= 0;
left_output_r <= 0;
right_output_r <= 0;
fifo_restart_r <= 0;
fifo_restart_l_r <= 0;

end else begin
state_r <= state_next;
left_sample_r <= left_sample_next;
right_sample_r <= right_sample_next;
left_output_r <= left_output_next;
right_output_r <= right_output_next;
fifo_restart_r <= fifo_restart_next;
fifo_restart_l_r <= fifo_restart_l_next;
end
end

Expand Down
2 changes: 1 addition & 1 deletion fpga/source/audio/psg.v
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ module psg(

// Audio output
output wire [15:0] left_audio,
output wire [15:0] right_audio) /* synthesis syn_hier = "hard" */;
output wire [15:0] right_audio);


//////////////////////////////////////////////////////////////////////////
Expand Down
14 changes: 13 additions & 1 deletion fpga/source/top.v
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Expand Up @@ -137,6 +137,8 @@ module top(
reg audio_mode_stereo_r, audio_mode_stereo_next;
reg audio_mode_16bit_r, audio_mode_16bit_next;
reg audio_fifo_reset_r, audio_fifo_reset_next;
reg audio_fifo_restart_r, audio_fifo_restart_next;
reg audio_fifo_loop_r, audio_fifo_loop_next;
wire audio_fifo_full;
reg [3:0] audio_pcm_volume_r, audio_pcm_volume_next;
reg [7:0] audio_fifo_wrdata_r, audio_fifo_wrdata_next;
Expand Down Expand Up @@ -316,6 +318,8 @@ module top(
audio_mode_stereo_next = audio_mode_stereo_r;
audio_mode_16bit_next = audio_mode_16bit_r;
audio_fifo_reset_next = 0;
audio_fifo_restart_next = 0;
audio_fifo_loop_next = audio_fifo_loop_r;
audio_pcm_volume_next = audio_pcm_volume_r;
audio_fifo_wrdata_next = audio_fifo_wrdata_r;
audio_fifo_write_next = 0;
Expand Down Expand Up @@ -469,7 +473,9 @@ module top(
end

if (do_write && access_addr == 5'h1B) begin
audio_fifo_reset_next = write_data[7];
audio_fifo_reset_next = write_data[7:6] == 2'b10;
audio_fifo_restart_next = write_data[6];
audio_fifo_loop_next = write_data[7:6] == 2'b11;
audio_mode_16bit_next = write_data[5];
audio_mode_stereo_next = write_data[4];
audio_pcm_volume_next = write_data[3:0];
Expand Down Expand Up @@ -539,6 +545,8 @@ module top(
audio_mode_stereo_r <= 0;
audio_mode_16bit_r <= 0;
audio_fifo_reset_r <= 0;
audio_fifo_restart_r <= 0;
audio_fifo_loop_r <= 0;
audio_pcm_volume_r <= 0;
audio_fifo_wrdata_r <= 0;
audio_fifo_write_r <= 0;
Expand Down Expand Up @@ -597,6 +605,8 @@ module top(
audio_mode_stereo_r <= audio_mode_stereo_next;
audio_mode_16bit_r <= audio_mode_16bit_next;
audio_fifo_reset_r <= audio_fifo_reset_next;
audio_fifo_restart_r <= audio_fifo_restart_next;
audio_fifo_loop_r <= audio_fifo_loop_next;
audio_pcm_volume_r <= audio_pcm_volume_next;
audio_fifo_wrdata_r <= audio_fifo_wrdata_next;
audio_fifo_write_r <= audio_fifo_write_next;
Expand Down Expand Up @@ -1177,6 +1187,8 @@ module top(

// Audio FIFO interface
.fifo_reset(audio_fifo_reset_r),
.fifo_restart(audio_fifo_restart_r),
.fifo_loop(audio_fifo_loop_r),
.fifo_wrdata(audio_fifo_wrdata_r),
.fifo_write(audio_fifo_write_r),
.fifo_full(audio_fifo_full),
Expand Down