Initial commit

.gitignore

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+boards/ZCU111/pynq_sdfec/
+boards/ZCU111/bitstreams/
+
+.Xil
+vivado.jou
+vivado.log
+
+*.log
+
+*.idea
+*.ipynb_checkpoints

LICENSE

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+Copyright (c) 2019, Xilinx
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+  this list of conditions and the following disclaimer in the documentation
+  and/or other materials provided with the distribution.
+
+* Neither the name of the copyright holder nor the names of its
+  contributors may be used to endorse or promote products derived from
+  this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Makefile

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+all: wheel
+
+wheel:
+	python3 setup.py bdist_wheel

README.md

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+# SDFEC-PYNQ
+
+This design offers an environment to evaluate the Soft Decision Forward Error
+Correction (SD-FEC) IPs using PYNQ and a ZCU111 board. Based on work by Andy Dow
+(Xilinx; Edinburgh), it allows us to play with a configurable data path
+including:
+
+  1. A data source including BPSK, QPSK, QAM-16, and QAM-64 modulation schemes
+  2. An encoding/decoding pair of SD-FEC blocks with a set of different LDPC
+     codes
+  3. An AWGN channel model with configurable noise power
+
+<div align="center">
+    <a href="https://github.com/Xilinx/SDFEC-PYNQ/blob/master/boards/ZCU111/notebooks/assets/notebook_preview.png">
+      <img src="https://github.com/Xilinx/SDFEC-PYNQ/blob/master/boards/ZCU111/notebooks/assets/notebook_preview.png" width="750px"/>
+    </a>
+</div>
+
+
+## Getting started
+
+This repository is only compatible with the [PYNQ image v2.4.1](https://github.com/Xilinx/PYNQ/releases) for [ZCU111](https://www.xilinx.com/products/boards-and-kits/zcu111.html).
+
+We supply pre-built wheels with all tagged releases. These can be installed
+directly with pip.
+
+```sh
+pip3 install https://github.com/Xilinx/SDFEC-PYNQ/releases/download/v1.0_$BOARD/rfsoc_sdfec-1.0-py3-none-any.whl
+```
+
+The wheel is just a self-contained archive, so we must ask the module to copy
+its notebooks to the filesystem after installation.
+
+```sh
+python3 -c 'import rfsoc_sdfec; rfsoc_sdfec.install_notebooks()'
+```
+
+The notebook should now be available in `rfsoc_sdfec/`.
+
+## Building the wheel
+
+> NOTE: This is built on an x86 PC with Vivado, not on the board!
+
+We release pre-built wheels for every tagged release. If you want to build your
+own wheel, this can be done from a Linux PC with Python3 and Vivado 2018.3
+installed. Clone this repo and use make to build the wheel:
+
+```sh
+git clone https://github.com/Xilinx/SDFEC-PYNQ.git
+cd SDFEC-PYNQ
+BOARD=ZCU111 make wheel
+```
+
+The wheel is built in the `dist` folder.
+
+## License 
+[BSD 3-Clause](https://github.com/Xilinx/SDFEC-PYNQ/blob/master/LICENSE)

boards/ZCU111/Makefile

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+design_name := sdfec_pynq
+bitfile := bitstreams/sdfec_pynq.bit
+
+all: $(bitfile)
+
+$(bitfile):
+	# some bash magic to retrieve LDPC codes and get them in a format required by the demo
+	$(shell cat $(XILINX_VIVADO)/data/ip/xilinx/sd_fec_v1_1/common_tcl/{docsis,wifi,5g_demo}_decode.yml | sed 's/_decode:/:/g' | sed '/skip_enc_compatibility: 1/d' | sed '/encode: false/d' > srcs/all_codes.txt)
+
+	vivado -mode batch -source create_project.tcl -notrace
+
+clean:
+	rm -rf $(design_name) ./srcs/all_codes.txt ./bitstreams *.jou *.log NA

boards/ZCU111/create_project.tcl

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+set proj_name "sdfec_pynq"
+set exdes_name "sd_fec_gen_ex"
+set exdes_dir "${proj_name}/sdfec_exdes/${exdes_name}"
+
+create_project -force $proj_name ./$proj_name -part xczu28dr-ffvg1517-2L-e
+
+create_ip -name sd_fec -vendor xilinx.com -library ip -version 1.1 -module_name sd_fec_gen
+set_property -dict [list CONFIG.Standard "Custom" \
+                         CONFIG.LDPC_Decode "true" \
+                         CONFIG.LDPC_Decode_Code_Definition "[pwd]/srcs/all_codes.txt" \
+                         CONFIG.DIN_Lanes 2 \
+                         CONFIG.Include_PS_Example_Design "true" \
+                         CONFIG.Example_Design_PS_Type "ZYNQ_UltraScale+_RFSoC" \
+                         CONFIG.Include_Encoder "true" \
+                         CONFIG.Build_SDK_Project "false"] [get_ips sd_fec_gen]
+
+open_example_project -in_process -force -dir ./${proj_name}/sdfec_exdes [get_ips sd_fec_gen]
+
+# change PS Master AXI width to 128 to conform with PYNQ requirements
+set_property -dict [list CONFIG.PSU__MAXIGP0__DATA_WIDTH {128}] [get_bd_cells zynq_ultra_ps]
+
+validate_bd_design
+save_bd_design
+
+add_files -fileset constrs_1 -norecurse ./srcs/zcu111_constraints.xdc
+
+set_property strategy Performance_ExplorePostRoutePhysOpt [get_runs impl_1]
+
+# change number of threads to suit your cpu
+launch_runs impl_1 -to_step write_bitstream -jobs 16
+wait_on_run impl_1
+
+# get bitstream and hwh files
+if {![file exists ./bitstreams/]} {
+	file mkdir ./bitstreams/
+	}
+
+file copy -force ./${exdes_dir}/${exdes_name}.runs/impl_1/ps_example_wrapper.bit ./bitstreams/${proj_name}.bit
+file copy -force ./${exdes_dir}/${exdes_name}.srcs/sources_1/bd/ps_example/hw_handoff/ps_example.hwh ./bitstreams/${proj_name}.hwh