[AIE2][AIE2P] Instruction select G_SELECT.

llvm/lib/Target/AIE/AIE2InstrPatterns.td

@@ -4,7 +4,7 @@
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
-// (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
+// (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
 //
 //===----------------------------------------------------------------------===//
 //
@@ -116,33 +116,6 @@ class SelectPat<ValueType type> :
 def : SelectPat<ptr0>;
 def : SelectPat<i32>;
 
-// For vector select, VSEL instruction is used, since it does select word by word
-// sel input is modified, "sel ? v1 : v2 is equivalent to vsel(sel-1, v1, v2)"
-// rs1(sel) is zero-extended from the original 1 bit type
-foreach vec256Ty = [v32i8, v16i16, v8i32] in {
-def : Pat<(vec256Ty (select (i32 eRS8:$rs1), VEC256:$rs2, VEC256:$rs3)),
-          (vec256Ty (EXTRACT_SUBREG (VSEL_32
-                     (v32i16 (REG_SEQUENCE VEC512, VEC256:$rs2, sub_256_lo)),
-                     (v32i16 (REG_SEQUENCE VEC512, VEC256:$rs3, sub_256_lo)),
-                     (ADD_add_r_ri eR:$rs1, (i32 -1))),
-                   sub_256_lo))>;
-}
-foreach vec512Ty = [v64i8, v32i16, v16i32] in {
-  def : Pat<(vec512Ty (select (i32 eRS8:$rs1), VEC512:$rs2, VEC512:$rs3)),
-            (vec512Ty (VSEL_32 VEC512:$rs2, VEC512:$rs3, (ADD_add_r_ri eR:$rs1, (i32 -1))))>;
-}
-foreach vec1024Ty = [v128i8, v64i16, v32i32] in {
-def : Pat<(vec1024Ty (select (i32 eRS8:$rs1), VEC1024:$rs2, VEC1024:$rs3)),
-          (REG_SEQUENCE VEC1024,
-             (VSEL_32 (v16i32 (EXTRACT_SUBREG VEC1024:$rs2, sub_512_lo)),
-                      (v16i32 (EXTRACT_SUBREG VEC1024:$rs3, sub_512_lo)),
-                      (ADD_add_r_ri eR:$rs1, (i32 -1))), sub_512_lo,
-             (VSEL_32 (v16i32 (EXTRACT_SUBREG VEC1024:$rs2, sub_512_hi)),
-                      (v16i32 (EXTRACT_SUBREG VEC1024:$rs3, sub_512_hi)),
-                      (ADD_add_r_ri eR:$rs1, (i32 -1))), sub_512_hi
-          )>;
-}
-
 class SelectNezPat<ValueType type> :
          Pat<(type (select (i32 (setne eR27:$rs1, (i32 0))), (type eR:$rs2), (type eR:$rs3))),
           (SELNEZ eR:$rs2, eR:$rs3, eR27:$rs1)>;

llvm/lib/Target/AIE/AIEBaseInstrPatterns.td

@@ -4,7 +4,7 @@
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
-// (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates
+// (c) Copyright 2024-2025 Advanced Micro Devices, Inc. or its affiliates
 //
 //===----------------------------------------------------------------------===//
 //
@@ -69,3 +69,11 @@ def : Pat<(vec1024Ty (and VEC1024:$src1, VEC1024:$src2)),
                         (v16i32 (EXTRACT_SUBREG VEC1024:$src2, sub_512_hi))), sub_512_hi
           )>;
 }
+
+// For vector select, VSEL instruction is used, since it does select word by word
+// sel input is modified, "sel ? v1 : v2 is equivalent to vsel(sel-1, v1, v2)"
+// rs1(sel) is zero-extended from the original 1 bit type
+foreach vec512Ty = [v64i8, v32i16, v16i32] in {
+  def : Pat<(vec512Ty (select (i32 eR:$rs1), VEC512:$rs2, VEC512:$rs3)),
+            (vec512Ty (VSEL_32 VEC512:$rs2, VEC512:$rs3, (ADD_add_r_ri eR:$rs1, (i32 -1))))>;
+}

llvm/test/CodeGen/AIE/GlobalISel/inst-select-select.mir

@@ -4,8 +4,10 @@
 # See https://llvm.org/LICENSE.txt for license information.
 # SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 #
-# (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
-# RUN: llc -mtriple aie -run-pass=instruction-select %s -verify-machineinstrs -o - | FileCheck %s
+# (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
+
+# RUN: llc -mtriple aie2 -run-pass=instruction-select %s -verify-machineinstrs -o - | FileCheck --check-prefix=AIE2 %s
+# RUN: llc -mtriple aie2p -run-pass=instruction-select %s -verify-machineinstrs -o - | FileCheck --check-prefix=AIE2P %s
 
 ---
 name: select_s32
@@ -15,12 +17,23 @@ regBankSelected: true
 body: |
   bb.0:
     liveins: $r6, $r7, $r8
-    ; CHECK-LABEL: name: select_s32
-    ; CHECK: [[COPY:%[0-9]+]]:gpr0 = COPY $r6
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r7
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $r8
-    ; CHECK-NEXT: [[ITE_NEZ:%[0-9]+]]:gpr = ITE_NEZ [[COPY1]], [[COPY2]], [[COPY]]
-    ; CHECK-NEXT: $r0 = COPY [[ITE_NEZ]]
+    ; AIE2-LABEL: name: select_s32
+    ; AIE2: liveins: $r6, $r7, $r8
+    ; AIE2-NEXT: {{  $}}
+    ; AIE2-NEXT: [[COPY:%[0-9]+]]:er27 = COPY $r6
+    ; AIE2-NEXT: [[COPY1:%[0-9]+]]:er = COPY $r7
+    ; AIE2-NEXT: [[COPY2:%[0-9]+]]:er = COPY $r8
+    ; AIE2-NEXT: [[SELNEZ:%[0-9]+]]:er = SELNEZ [[COPY1]], [[COPY2]], [[COPY]]
+    ; AIE2-NEXT: $r0 = COPY [[SELNEZ]]
+    ;
+    ; AIE2P-LABEL: name: select_s32
+    ; AIE2P: liveins: $r6, $r7, $r8
+    ; AIE2P-NEXT: {{  $}}
+    ; AIE2P-NEXT: [[COPY:%[0-9]+]]:mr27_select = COPY $r6
+    ; AIE2P-NEXT: [[COPY1:%[0-9]+]]:er = COPY $r7
+    ; AIE2P-NEXT: [[COPY2:%[0-9]+]]:er = COPY $r8
+    ; AIE2P-NEXT: [[SEL_NEZ:%[0-9]+]]:er = SEL_NEZ [[COPY1]], [[COPY2]], [[COPY]]
+    ; AIE2P-NEXT: $r0 = COPY [[SEL_NEZ]]
     %0:gprregbank(s32) = COPY $r6
     %1:gprregbank(s32) = COPY $r7
     %2:gprregbank(s32) = COPY $r8
@@ -36,14 +49,27 @@ regBankSelected: true
 body: |
   bb.0:
     liveins: $p0, $p1, $r6
-    ; CHECK-LABEL: name: select_p0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr0 = COPY $r6
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ptr = COPY $p0
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:ptr = COPY $p1
-    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY [[COPY1]]
-    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY [[COPY2]]
-    ; CHECK-NEXT: [[ITE_NEZ:%[0-9]+]]:gpr = ITE_NEZ [[COPY3]], [[COPY4]], [[COPY]]
-    ; CHECK-NEXT: $p0 = COPY [[ITE_NEZ]]
+    ; AIE2-LABEL: name: select_p0
+    ; AIE2: liveins: $p0, $p1, $r6
+    ; AIE2-NEXT: {{  $}}
+    ; AIE2-NEXT: [[COPY:%[0-9]+]]:er27 = COPY $r6
+    ; AIE2-NEXT: [[COPY1:%[0-9]+]]:ep = COPY $p0
+    ; AIE2-NEXT: [[COPY2:%[0-9]+]]:ep = COPY $p1
+    ; AIE2-NEXT: [[COPY3:%[0-9]+]]:er = COPY [[COPY1]]
+    ; AIE2-NEXT: [[COPY4:%[0-9]+]]:er = COPY [[COPY2]]
+    ; AIE2-NEXT: [[SELNEZ:%[0-9]+]]:er = SELNEZ [[COPY3]], [[COPY4]], [[COPY]]
+    ; AIE2-NEXT: $p0 = COPY [[SELNEZ]]
+    ;
+    ; AIE2P-LABEL: name: select_p0
+    ; AIE2P: liveins: $p0, $p1, $r6
+    ; AIE2P-NEXT: {{  $}}
+    ; AIE2P-NEXT: [[COPY:%[0-9]+]]:mr27_select = COPY $r6
+    ; AIE2P-NEXT: [[COPY1:%[0-9]+]]:ep = COPY $p0
+    ; AIE2P-NEXT: [[COPY2:%[0-9]+]]:ep = COPY $p1
+    ; AIE2P-NEXT: [[COPY3:%[0-9]+]]:er = COPY [[COPY1]]
+    ; AIE2P-NEXT: [[COPY4:%[0-9]+]]:er = COPY [[COPY2]]
+    ; AIE2P-NEXT: [[SEL_NEZ:%[0-9]+]]:er = SEL_NEZ [[COPY3]], [[COPY4]], [[COPY]]
+    ; AIE2P-NEXT: $p0 = COPY [[SEL_NEZ]]
     %0:gprregbank(s32) = COPY $r6
     %1:ptrregbank(p0) = COPY $p0
     %2:ptrregbank(p0) = COPY $p1
@@ -52,3 +78,40 @@ body: |
     %5:gprregbank(p0) = G_SELECT %0, %3, %4
     $p0 = COPY %5
 ...
+
+---
+name: select_v512
+legalized: true
+regBankSelected: true
+body: |
+  bb.1.entry:
+    liveins: $r0, $x2, $x4
+    ; AIE2-LABEL: name: select_v512
+    ; AIE2: liveins: $r0, $x2, $x4
+    ; AIE2-NEXT: {{  $}}
+    ; AIE2-NEXT: [[COPY:%[0-9]+]]:er = COPY $r0
+    ; AIE2-NEXT: [[COPY1:%[0-9]+]]:vec512 = COPY $x2
+    ; AIE2-NEXT: [[COPY2:%[0-9]+]]:vec512 = COPY $x4
+    ; AIE2-NEXT: [[ADD_add_r_ri:%[0-9]+]]:ers8 = ADD_add_r_ri [[COPY]], -1, implicit-def dead $srcarry
+    ; AIE2-NEXT: [[VSEL_32_:%[0-9]+]]:vec512 = VSEL_32 [[COPY1]], [[COPY2]], [[ADD_add_r_ri]]
+    ; AIE2-NEXT: $x0 = COPY [[VSEL_32_]]
+    ; AIE2-NEXT: PseudoRET implicit $lr, implicit $x0
+    ;
+    ; AIE2P-LABEL: name: select_v512
+    ; AIE2P: liveins: $r0, $x2, $x4
+    ; AIE2P-NEXT: {{  $}}
+    ; AIE2P-NEXT: [[COPY:%[0-9]+]]:er = COPY $r0
+    ; AIE2P-NEXT: [[COPY1:%[0-9]+]]:vec512 = COPY $x2
+    ; AIE2P-NEXT: [[COPY2:%[0-9]+]]:vec512 = COPY $x4
+    ; AIE2P-NEXT: [[ADD_add_r_ri:%[0-9]+]]:ers16 = ADD_add_r_ri [[COPY]], -1, implicit-def dead $srcarry
+    ; AIE2P-NEXT: [[VSEL_32_:%[0-9]+]]:vec512 = VSEL_32 [[COPY1]], [[COPY2]], [[ADD_add_r_ri]]
+    ; AIE2P-NEXT: $x0 = COPY [[VSEL_32_]]
+    ; AIE2P-NEXT: PseudoRET implicit $lr, implicit $x0
+    %4:gprregbank(s32) = COPY $r0
+    %5:gprregbank(s32) = G_ASSERT_ZEXT %4:gprregbank, 1
+    %2:vregbank(<16 x s32>) = COPY $x2
+    %3:vregbank(<16 x s32>) = COPY $x4
+    %0:vregbank(<16 x s32>) = G_SELECT %5:gprregbank(s32), %2:vregbank, %3:vregbank
+    $x0 = COPY %0:vregbank(<16 x s32>)
+    PseudoRET implicit $lr, implicit $x0
+...