[AIE2P] RegBankSelect G_UNMERGE_VALUES for ACC1024

Xilinx · Jan 30, 2025 · 512188c · 512188c
1 parent ce82b59
commit 512188c
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Showing 2 changed files with 17 additions and 6 deletions.
diff --git a/llvm/lib/Target/AIE/aie2p/AIE2PRegisterBankInfo.cpp b/llvm/lib/Target/AIE/aie2p/AIE2PRegisterBankInfo.cpp
@@ -854,16 +854,28 @@ AIE2PRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
                                                          OpRegBankIdx);
   }
   case TargetOpcode::G_UNMERGE_VALUES: {
+    assert(MI.getNumOperands() == 3 &&
+           "Unsupported number of operands for G_UNMERGE_VALUES\n");
     const Register SrcReg = MI.getOperand(2).getReg();
     const LLT SrcTy = MRI.getType(SrcReg);
-    if (SrcTy.getSizeInBits() == 2048) {
+
+    auto *RB = getRegBank(SrcReg, MRI, TRI);
+    if ((RB == &AIE2P::AccRegBank) &&
+        (SrcTy.getSizeInBits() == 1024 || SrcTy.getSizeInBits() == 2048)) {
+      const LLT HalfSrcTy = SrcTy.divide(2);
+      const unsigned HalfSrcTySize = HalfSrcTy.getSizeInBits();
       return getInstructionMapping(
           /*ID*/ 1, /*Cost*/ 1,
-          getOperandsMapping({getValueMapping(PMI_ACC1024, 1024),
-                              getValueMapping(PMI_ACC1024, 1024),
-                              getValueMapping(PMI_ACC2048, 2048)}),
+          getOperandsMapping(
+              {getValueMapping(getAccPartialMappingIdx(HalfSrcTy),
+                               HalfSrcTySize),
+               getValueMapping(getAccPartialMappingIdx(HalfSrcTy),
+                               HalfSrcTySize),
+               getValueMapping(getAccPartialMappingIdx(SrcTy),
+                               SrcTy.getSizeInBits())}),
           /*NumOperands*/ 3);
     }
+
     if (SrcTy.getSizeInBits() == 512) {
       return getInstructionMapping(
           /*ID*/ 1, /*Cost*/ 1,

diff --git a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/regbankselect-unmerge-values.mir b/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/regbankselect-unmerge-values.mir
@@ -71,8 +71,7 @@ body:             |
     ; CHECK: liveins: $cml0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:accregbank(<2 x s512>) = COPY $cml0
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vregbank(<2 x s512>) = COPY [[COPY]](<2 x s512>)
-    ; CHECK-NEXT: [[UV:%[0-9]+]]:vregbank(s512), [[UV1:%[0-9]+]]:vregbank(s512) = G_UNMERGE_VALUES [[COPY1]](<2 x s512>)
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:accregbank(s512), [[UV1:%[0-9]+]]:accregbank(s512) = G_UNMERGE_VALUES [[COPY]](<2 x s512>)
     ; CHECK-NEXT: $bmll0 = COPY [[UV]](s512)
     ; CHECK-NEXT: $bmll2 = COPY [[UV1]](s512)
     %0:_(<2 x s512>) = COPY $cml0