[AIE2][AIE2P] Move selection of G_AIE_[ZS]EXT_EXTRACT_VECTOR_ELT to T…

…ableGen patterns

For AIE2, this is NFC. For AIE2P, we now benefit from patterns supporting constant indices.

llvm/lib/Target/AIE/AIE2.h

@@ -34,7 +34,6 @@ class MachineInstr;
 class MachineOperand;
 class PassRegistry;
 
-FunctionPass *createAIE2ISelDag(TargetMachine &TM);
 FunctionPass *createAIE2PreLegalizerCombiner();
 FunctionPass *createAIE2PostLegalizerCustomCombiner();
 FunctionPass *createAIE2PostLegalizerGenericCombiner();

llvm/lib/Target/AIE/AIE2InstrPatterns.td

@@ -1068,3 +1068,8 @@ def : PatInaccessibleMem<(int_aie2_clr16f_conf),
 // DIVS
 def : Pat<(int_aie2_divs eR31:$sd_in, eR:$src0, eR:$src1),
           (DIVS eR31:$sd_in, eR:$src0, eR:$src1)>;
+
+// G_AIE_[SZ]EXT_EXTRACT_VECTOR_ELT
+defm : Extract_512<i32, v64i8, (i32 eR:$idx), VEXTRACT_D8, VEXTRACT_S8>;
+defm : Extract_512<i32, v32i16, (i32 eR:$idx), VEXTRACT_D16, VEXTRACT_S16>;
+defm : Extract_512<i32, v16i32, (i32 eR:$idx), VEXTRACT_D32, VEXTRACT_S32>;

llvm/lib/Target/AIE/AIE2InstructionSelector.cpp

@@ -103,8 +103,6 @@ class AIE2InstructionSelector : public AIEBaseInstructionSelector {
   bool selectG_AIE_STORE_CONV(MachineInstr &StoreI, MachineRegisterInfo &MRI);
   bool selectG_AIE_STORE_PACK(MachineInstr &StoreI, MachineRegisterInfo &MRI);
   bool selectStartLoop(MachineInstr &I, MachineRegisterInfo &MRI);
-  bool selectG_AIE_EXTRACT_VECTOR_ELT(MachineInstr &I,
-                                      MachineRegisterInfo &MRI);
   bool selectG_AIE_INSERT_VECTOR_ELT(MachineInstr &I, MachineRegisterInfo &MRI);
   bool selectG_AIE_PAD_VECTOR_UNDEF(MachineInstr &I, MachineOperand &DstReg,
                                     MachineOperand &SrcReg,
@@ -452,9 +450,6 @@ bool AIE2InstructionSelector::select(MachineInstr &I) {
   case AIE2::G_AIE_POSTINC_3D_SEXTLOAD:
   case AIE2::G_AIE_POSTINC_3D_ZEXTLOAD:
     return selectG_AIE_LOAD_STORE(I, MRI);
-  case AIE2::G_AIE_ZEXT_EXTRACT_VECTOR_ELT:
-  case AIE2::G_AIE_SEXT_EXTRACT_VECTOR_ELT:
-    return selectG_AIE_EXTRACT_VECTOR_ELT(I, MRI);
   case AIE2::G_AIE_INSERT_VECTOR_ELT:
     return selectG_AIE_INSERT_VECTOR_ELT(I, MRI);
   case AIE2::G_AIE_PAD_VECTOR_UNDEF:
@@ -3755,28 +3750,6 @@ createOpcodeCondRegPair(unsigned EltSize, Register LtReg, MachineIRBuilder &MIB,
   return std::make_pair(Opcode, SelReg);
 }
 
-static unsigned getExtractVecEltOpcode(unsigned EltSize, unsigned InstOpcode) {
-  unsigned Opcode = 0;
-  bool IsZextExtVecElt = InstOpcode == AIE2::G_AIE_ZEXT_EXTRACT_VECTOR_ELT;
-  switch (EltSize) {
-  case 8:
-    Opcode = IsZextExtVecElt ? AIE2::VEXTRACT_D8 : AIE2::VEXTRACT_S8;
-    break;
-  case 16:
-    Opcode = IsZextExtVecElt ? AIE2::VEXTRACT_D16 : AIE2::VEXTRACT_S16;
-    break;
-  case 32:
-    Opcode = IsZextExtVecElt ? AIE2::VEXTRACT_D32 : AIE2::VEXTRACT_S32;
-    break;
-  // there is no AIE vector with elt size 64, VEXTRACT_D64/VEXTRACT_S64 is
-  // selected only when the extracted value is another vector of size 64-bit.
-  default:
-    llvm_unreachable("Unexpected Extracted Vector Element Size");
-  }
-  assert(Opcode != 0 && "Expected a NonZero Opcode");
-  return Opcode;
-}
-
 static unsigned getInsertVecEltOpcode(unsigned EltSize, unsigned InstOpcode) {
   switch (EltSize) {
   case 8:
@@ -3931,24 +3904,6 @@ static SelSrcAndIdx getExtractOrInsertVectorEltInputs(
   return SelSrcIdx;
 }
 
-bool AIE2InstructionSelector::selectG_AIE_EXTRACT_VECTOR_ELT(
-    MachineInstr &I, MachineRegisterInfo &MRI) {
-  MachineOperand &RegOp0 = I.getOperand(1);
-  Register DstReg = I.getOperand(0).getReg();
-  Register SrcReg0 = RegOp0.getReg();
-  LLT SrcVecTy = MRI.getType(SrcReg0);
-  LLT SrcEltTy = SrcVecTy.getElementType();
-  unsigned EltSize = SrcEltTy.getSizeInBits();
-  SelSrcAndIdx SelSrcIdx =
-      getExtractOrInsertVectorEltInputs(I, TRI, MRI, TII, RBI, MIB);
-  unsigned Opcode = getExtractVecEltOpcode(EltSize, I.getOpcode());
-  MachineInstrBuilder MI = MIB.buildInstr(Opcode, {DstReg}, {})
-                               .addReg(SelSrcIdx.SrcReg)
-                               .addReg(SelSrcIdx.IdxReg);
-  I.eraseFromParent();
-  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
-}
-
 bool AIE2InstructionSelector::selectG_AIE_INSERT_VECTOR_ELT(
     MachineInstr &I, MachineRegisterInfo &MRI) {
   Register DstVecReg = I.getOperand(0).getReg();

llvm/lib/Target/AIE/AIE2TargetMachine.cpp

@@ -220,15 +220,6 @@ AIE2TargetMachine::getTargetTransformInfo(const Function &F) const {
   return TargetTransformInfo(AIE2TTIImpl(this, F));
 }
 
-bool AIE2PassConfig::addInstSelector() {
-  if (AIEDumpArtifacts)
-    addPass(createMachineFunctionDumperPass(/*Suffix=*/"before-isel"));
-  addPass(createAIE2ISelDag(getAIETargetMachine()));
-  if (AIEDumpArtifacts)
-    addPass(createMachineFunctionDumperPass(/*Suffix=*/"after-isel"));
-  return false;
-}
-
 unsigned
 AIE2TargetMachine::getAddressSpaceForPseudoSourceKind(unsigned Kind) const {
   switch (Kind) {

llvm/lib/Target/AIE/AIE2TargetMachine.h

@@ -57,7 +57,6 @@ class AIE2PassConfig : public AIEBasePassConfig {
 
   bool addPreISel() override;
   void addPreEmitPass() override;
-  bool addInstSelector() override;
   bool addGlobalInstructionSelect() override;
   void addPreRegAlloc() override;
   bool addRegAssignAndRewriteOptimized() override;

llvm/lib/Target/AIE/AIEBaseInstrPatterns.td

@@ -77,3 +77,21 @@ foreach vec512Ty = [v64i8, v32i16, v16i32] in {
   def : Pat<(vec512Ty (select (i32 eR:$rs1), VEC512:$rs2, VEC512:$rs3)),
             (vec512Ty (VSEL_32 VEC512:$rs2, VEC512:$rs3, (ADD_add_r_ri eR:$rs1, (i32 -1))))>;
 }
+
+// Make our generic extract vector elt instructions available to TableGen patterns.
+def vextract_zext : SDNode<"G_AIE_ZEXT_EXTRACT_VECTOR_ELT",
+                          SDTypeProfile<1, 2, [SDTCisInt<0>,SDTCisVec<1>, SDTCisInt<2>]>>;
+def : GINodeEquiv<G_AIE_ZEXT_EXTRACT_VECTOR_ELT, vextract_zext>;
+
+def vextract_sext : SDNode<"G_AIE_SEXT_EXTRACT_VECTOR_ELT",
+                          SDTypeProfile<1, 2, [SDTCisInt<0>,SDTCisVec<1>, SDTCisInt<2>]>>;
+def : GINodeEquiv<G_AIE_SEXT_EXTRACT_VECTOR_ELT, vextract_sext>;
+
+class Extr512Pat<ValueType DstTy, ValueType SrcTy, dag Idx, SDNode Op, Instruction Inst> :
+    Pat<(DstTy (Op SrcTy:$src1, Idx)),
+        (Inst SrcTy:$src1, Idx)>;
+
+multiclass Extract_512<ValueType DstTy, ValueType SrcTy, dag Idx, Instruction UnsignedOpc, Instruction SignedOpc> {
+  def : Extr512Pat<DstTy, SrcTy, Idx, vextract_zext, UnsignedOpc>;
+  def : Extr512Pat<DstTy, SrcTy, Idx, vextract_sext, SignedOpc>;
+}

llvm/lib/Target/AIE/CMakeLists.txt

@@ -33,7 +33,6 @@ tablegen(LLVM AIE2GenPostLegalizerGIGenericCombiner.inc -gen-global-isel-combine
 tablegen(LLVM AIE2GenPostLegalizerGICustomCombiner.inc -gen-global-isel-combiner
               -combiners="AIE2PostLegalizerCustomCombiner")
 tablegen(LLVM AIE2GenCallingConv.inc -gen-callingconv)
-tablegen(LLVM AIE2GenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM AIE2GenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM AIE2GenFormats.inc -gen-instr-format)
 tablegen(LLVM AIE2GenInstrInfo.inc -gen-instr-info -base-instrinfo-class AIEBaseInstrInfo)
@@ -129,7 +128,6 @@ add_llvm_target(AIECodeGen
    AIE2FrameLowering.cpp
    AIE2InstrInfo.cpp
    AIE2InstructionSelector.cpp
-   AIE2ISelDAGToDAG.cpp
    AIE2ISelLowering.cpp
    AIE2LegalizerInfo.cpp
    AIE2PostLegalizerCustomCombiner.cpp

llvm/lib/Target/AIE/aie2p/AIE2PInstrPatterns.td

@@ -1096,3 +1096,14 @@ foreach Ty = [v64i8, v32i16, v16i32, v8i64] in {
 def : Pat<(Ty (vshift_node VEC512:$src1, VEC512:$src2, (i32 eR:$shift))),
           (VSHIFT VEC512:$src1, VEC512:$src2, eR:$shift)>;
 }
+
+// G_AIE_[SZ]EXT_EXTRACT_VECTOR_ELT
+defm : Extract_512<i32, v64i8, (i32 eR:$idx), VEXTRACT_8_vec_extract_r_vaddSign0, VEXTRACT_8_vec_extract_r_vaddSign1>;
+defm : Extract_512<i32, v32i16, (i32 eR:$idx), VEXTRACT_16_vec_extract_r_vaddSign0, VEXTRACT_16_vec_extract_r_vaddSign1>;
+defm : Extract_512<i32, v16i32, (i32 eR:$idx), VEXTRACT_32_vec_extract_r_vaddSign0, VEXTRACT_32_vec_extract_r_vaddSign1>;
+defm : Extract_512<i64, v8i64, (i32 eR:$idx), VEXTRACT_64_vec_extract_r_vaddSign0, VEXTRACT_64_vec_extract_r_vaddSign1>;
+
+defm : Extract_512<i32, v64i8, (i32 c6u:$idx), VEXTRACT_8_vec_extract_imm_vaddSign0, VEXTRACT_8_vec_extract_imm_vaddSign1>;
+defm : Extract_512<i32, v32i16, (i32 c6u:$idx), VEXTRACT_16_vec_extract_imm_vaddSign0, VEXTRACT_16_vec_extract_imm_vaddSign1>;
+defm : Extract_512<i32, v16i32, (i32 c6u:$idx), VEXTRACT_32_vec_extract_imm_vaddSign0, VEXTRACT_32_vec_extract_imm_vaddSign1>;
+defm : Extract_512<i64, v8i64, (i32 c6u:$idx), VEXTRACT_64_vec_extract_imm_vaddSign0, VEXTRACT_64_vec_extract_imm_vaddSign1>;

llvm/lib/Target/AIE/aie2p/AIE2PInstructionSelector.cpp

@@ -58,8 +58,6 @@ class AIE2PInstructionSelector : public AIEBaseInstructionSelector {
                             unsigned crUPSModeVal);
   bool selectG_AIE_ADD_VECTOR_ELT_HI(MachineInstr &I, MachineRegisterInfo &MRI);
   bool selectVCONVbfp16(MachineInstr &I, MachineRegisterInfo &MRI);
-  bool selectG_AIE_EXTRACT_VECTOR_ELT(MachineInstr &I,
-                                      MachineRegisterInfo &MRI);
   bool selectG_AIE_INSERT_VECTOR_ELT(MachineInstr &I, MachineRegisterInfo &MRI);
   bool selectG_AIE_PAD_VECTOR_UNDEF(MachineInstr &I, MachineOperand &DstReg,
                                     MachineOperand &SrcReg,
@@ -427,9 +425,6 @@ bool AIE2PInstructionSelector::select(MachineInstr &I) {
     return selectG_UNMERGE_VALUES(MIB, I, MRI);
   case AIE2P::G_AIE_ADD_VECTOR_ELT_HI:
     return selectG_AIE_ADD_VECTOR_ELT_HI(I, MRI);
-  case AIE2P::G_AIE_ZEXT_EXTRACT_VECTOR_ELT:
-  case AIE2P::G_AIE_SEXT_EXTRACT_VECTOR_ELT:
-    return selectG_AIE_EXTRACT_VECTOR_ELT(I, MRI);
   case AIE2P::G_AIE_INSERT_VECTOR_ELT:
     return selectG_AIE_INSERT_VECTOR_ELT(I, MRI);
   case AIE2P::G_AIE_BROADCAST_VECTOR:
@@ -818,32 +813,6 @@ struct SelSrcAndIdx {
 };
 
 } // end anonymous namespace
-static unsigned getExtractVecEltOpcode(unsigned EltSize, unsigned InstOpcode) {
-  unsigned Opcode = 0;
-  bool IsZextExtVecElt = InstOpcode == AIE2P::G_AIE_ZEXT_EXTRACT_VECTOR_ELT;
-  switch (EltSize) {
-  case 8:
-    Opcode = IsZextExtVecElt ? AIE2P::VEXTRACT_8_vec_extract_r_vaddSign0
-                             : AIE2P::VEXTRACT_8_vec_extract_r_vaddSign1;
-    break;
-  case 16:
-    Opcode = IsZextExtVecElt ? AIE2P::VEXTRACT_16_vec_extract_r_vaddSign0
-                             : AIE2P::VEXTRACT_16_vec_extract_r_vaddSign1;
-    break;
-  case 32:
-    Opcode = IsZextExtVecElt ? AIE2P::VEXTRACT_32_vec_extract_r_vaddSign0
-                             : AIE2P::VEXTRACT_32_vec_extract_r_vaddSign1;
-    break;
-  case 64:
-    Opcode = IsZextExtVecElt ? AIE2P::VEXTRACT_64_vec_extract_r_vaddSign0
-                             : AIE2P::VEXTRACT_64_vec_extract_r_vaddSign1;
-    break;
-  default:
-    llvm_unreachable("Unexpected Extracted Vector Element Size");
-  }
-  assert(Opcode != 0 && "Expected a NonZero Opcode");
-  return Opcode;
-}
 
 static unsigned getInsertVecEltOpcode(unsigned EltSize, unsigned InstOpcode) {
   switch (EltSize) {
@@ -1189,24 +1158,6 @@ static SelSrcAndIdx getExtractOrInsertVectorEltInputs(
   return SelSrcIdx;
 }
 
-bool AIE2PInstructionSelector::selectG_AIE_EXTRACT_VECTOR_ELT(
-    MachineInstr &I, MachineRegisterInfo &MRI) {
-  MachineOperand &RegOp0 = I.getOperand(1);
-  Register DstReg = I.getOperand(0).getReg();
-  Register SrcReg0 = RegOp0.getReg();
-  LLT SrcVecTy = MRI.getType(SrcReg0);
-  LLT SrcEltTy = SrcVecTy.getElementType();
-  unsigned EltSize = SrcEltTy.getSizeInBits();
-  SelSrcAndIdx SelSrcIdx =
-      getExtractOrInsertVectorEltInputs(I, TRI, MRI, TII, RBI, MIB);
-  unsigned Opcode = getExtractVecEltOpcode(EltSize, I.getOpcode());
-  MachineInstrBuilder MI = MIB.buildInstr(Opcode, {DstReg}, {})
-                               .addReg(SelSrcIdx.SrcReg)
-                               .addReg(SelSrcIdx.IdxReg);
-  I.eraseFromParent();
-  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
-}
-
 bool AIE2PInstructionSelector::selectG_AIE_INSERT_VECTOR_ELT(
     MachineInstr &I, MachineRegisterInfo &MRI) {
   Register DstVecReg = I.getOperand(0).getReg();

llvm/test/CodeGen/AIE/GlobalISel/inst-select-extract-vector-elem.mir

@@ -30,9 +30,8 @@ body:             |
     ; AIE2P: liveins: $x0
     ; AIE2P-NEXT: {{  $}}
     ; AIE2P-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY $x0
-    ; AIE2P-NEXT: [[MOV_RLC_imm11_pseudo:%[0-9]+]]:er = MOV_RLC_imm11_pseudo 1
-    ; AIE2P-NEXT: [[VEXTRACT_16_vec_extract_r_vaddSign0_:%[0-9]+]]:er = VEXTRACT_16_vec_extract_r_vaddSign0 [[COPY]], [[MOV_RLC_imm11_pseudo]], implicit $vaddsign0
-    ; AIE2P-NEXT: $r0 = COPY [[VEXTRACT_16_vec_extract_r_vaddSign0_]]
+    ; AIE2P-NEXT: [[VEXTRACT_16_vec_extract_imm_vaddSign0_:%[0-9]+]]:er = VEXTRACT_16_vec_extract_imm_vaddSign0 [[COPY]], 1, implicit $vaddsign0
+    ; AIE2P-NEXT: $r0 = COPY [[VEXTRACT_16_vec_extract_imm_vaddSign0_]]
     ; AIE2P-NEXT: PseudoRET implicit $lr, implicit $r0
     %1:vregbank(<32 x s16>) = COPY $x0
     %2:gprregbank(s32) = G_CONSTANT i32 1
@@ -63,9 +62,8 @@ body:             |
     ; AIE2P: liveins: $x0
     ; AIE2P-NEXT: {{  $}}
     ; AIE2P-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY $x0
-    ; AIE2P-NEXT: [[MOV_RLC_imm11_pseudo:%[0-9]+]]:er = MOV_RLC_imm11_pseudo 1
-    ; AIE2P-NEXT: [[VEXTRACT_16_vec_extract_r_vaddSign1_:%[0-9]+]]:er = VEXTRACT_16_vec_extract_r_vaddSign1 [[COPY]], [[MOV_RLC_imm11_pseudo]], implicit $vaddsign1
-    ; AIE2P-NEXT: $r0 = COPY [[VEXTRACT_16_vec_extract_r_vaddSign1_]]
+    ; AIE2P-NEXT: [[VEXTRACT_16_vec_extract_imm_vaddSign1_:%[0-9]+]]:er = VEXTRACT_16_vec_extract_imm_vaddSign1 [[COPY]], 1, implicit $vaddsign1
+    ; AIE2P-NEXT: $r0 = COPY [[VEXTRACT_16_vec_extract_imm_vaddSign1_]]
     ; AIE2P-NEXT: PseudoRET implicit $lr, implicit $r0
     %1:vregbank(<32 x s16>) = COPY $x0
     %2:gprregbank(s32) = G_CONSTANT i32 1
@@ -96,9 +94,8 @@ body:             |
     ; AIE2P: liveins: $x0
     ; AIE2P-NEXT: {{  $}}
     ; AIE2P-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY $x0
-    ; AIE2P-NEXT: [[MOV_RLC_imm11_pseudo:%[0-9]+]]:er = MOV_RLC_imm11_pseudo 1
-    ; AIE2P-NEXT: [[VEXTRACT_8_vec_extract_r_vaddSign1_:%[0-9]+]]:er = VEXTRACT_8_vec_extract_r_vaddSign1 [[COPY]], [[MOV_RLC_imm11_pseudo]], implicit $vaddsign1
-    ; AIE2P-NEXT: $r0 = COPY [[VEXTRACT_8_vec_extract_r_vaddSign1_]]
+    ; AIE2P-NEXT: [[VEXTRACT_8_vec_extract_imm_vaddSign1_:%[0-9]+]]:er = VEXTRACT_8_vec_extract_imm_vaddSign1 [[COPY]], 1, implicit $vaddsign1
+    ; AIE2P-NEXT: $r0 = COPY [[VEXTRACT_8_vec_extract_imm_vaddSign1_]]
     ; AIE2P-NEXT: PseudoRET implicit $lr, implicit $r0
     %1:vregbank(<64 x s8>) = COPY $x0
     %2:gprregbank(s32) = G_CONSTANT i32 1
@@ -129,9 +126,8 @@ body:             |
     ; AIE2P: liveins: $x0
     ; AIE2P-NEXT: {{  $}}
     ; AIE2P-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY $x0
-    ; AIE2P-NEXT: [[MOV_RLC_imm11_pseudo:%[0-9]+]]:er = MOV_RLC_imm11_pseudo 1
-    ; AIE2P-NEXT: [[VEXTRACT_8_vec_extract_r_vaddSign0_:%[0-9]+]]:er = VEXTRACT_8_vec_extract_r_vaddSign0 [[COPY]], [[MOV_RLC_imm11_pseudo]], implicit $vaddsign0
-    ; AIE2P-NEXT: $r0 = COPY [[VEXTRACT_8_vec_extract_r_vaddSign0_]]
+    ; AIE2P-NEXT: [[VEXTRACT_8_vec_extract_imm_vaddSign0_:%[0-9]+]]:er = VEXTRACT_8_vec_extract_imm_vaddSign0 [[COPY]], 1, implicit $vaddsign0
+    ; AIE2P-NEXT: $r0 = COPY [[VEXTRACT_8_vec_extract_imm_vaddSign0_]]
     ; AIE2P-NEXT: PseudoRET implicit $lr, implicit $r0
     %1:vregbank(<64 x s8>) = COPY $x0
     %2:gprregbank(s32) = G_CONSTANT i32 1
@@ -162,9 +158,8 @@ body:             |
     ; AIE2P: liveins: $x0
     ; AIE2P-NEXT: {{  $}}
     ; AIE2P-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY $x0
-    ; AIE2P-NEXT: [[MOV_RLC_imm11_pseudo:%[0-9]+]]:er = MOV_RLC_imm11_pseudo 1
-    ; AIE2P-NEXT: [[VEXTRACT_32_vec_extract_r_vaddSign1_:%[0-9]+]]:er = VEXTRACT_32_vec_extract_r_vaddSign1 [[COPY]], [[MOV_RLC_imm11_pseudo]], implicit $vaddsign1
-    ; AIE2P-NEXT: $r0 = COPY [[VEXTRACT_32_vec_extract_r_vaddSign1_]]
+    ; AIE2P-NEXT: [[VEXTRACT_32_vec_extract_imm_vaddSign1_:%[0-9]+]]:er = VEXTRACT_32_vec_extract_imm_vaddSign1 [[COPY]], 1, implicit $vaddsign1
+    ; AIE2P-NEXT: $r0 = COPY [[VEXTRACT_32_vec_extract_imm_vaddSign1_]]
     ; AIE2P-NEXT: PseudoRET implicit $lr, implicit $r0
     %1:vregbank(<16 x s32>) = COPY $x0
     %2:gprregbank(s32) = G_CONSTANT i32 1