Fix the .CST generation in the unpacker (#73)

Signed-off-by: YRabbit <[email protected]>
YosysHQ · Dec 15, 2021 · b860eaa · b860eaa
1 parent 60517e2
commit b860eaa
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/apycula/gowin_unpack.py b/apycula/gowin_unpack.py
@@ -246,7 +246,7 @@ def tile2verilog(dbrow, dbcol, bels, pips, clock_pips, mod, cfg, cst, db):
                 lut.portmap['I3'] = f"R{row}C{col}_D{idx}"
                 mod.wires.update(lut.portmap.values())
                 mod.primitives[name] = lut
-                cst.cells[name] = f"R{row}C{col}[{int(idx) // 2}][{_sides[int(idx) % 2]}]"
+                cst.cells[name] = (row, col, int(idx) // 2, _sides[int(idx) % 2])
             make_muxes(row, col, idx, db, mod)
         elif typ == "ALU":
             print(flags)
@@ -291,7 +291,7 @@ def tile2verilog(dbrow, dbcol, bels, pips, clock_pips, mod, cfg, cst, db):
                 dff.portmap[port] = f"R{row}C{col}_LSR{idx//2}"
             mod.wires.update(dff.portmap.values())
             mod.primitives[name] = dff
-            cst.cells[name] = f"R{row}C{col}[{int(idx) // 2}][{_sides[int(idx) % 2]}]"
+            cst.cells[name] = (row, col, int(idx) // 2, _sides[int(idx) % 2])
         elif typ == "IOB":
             try:
                 kind, = flags.intersection(iobmap.keys())