Remove unused imports.

adkian-sifive · Sep 30, 2020 · 66a60e5 · 66a60e5
1 parent 0a5e2e8
commit 66a60e5
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Showing 136 changed files with 37 additions and 210 deletions.
diff --git a/src/main/scala/amba/ahb/AHBLite.scala b/src/main/scala/amba/ahb/AHBLite.scala
@@ -5,7 +5,6 @@ package freechips.rocketchip.amba.ahb
 import Chisel._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.tilelink._
 
 class AHBLite()(implicit p: Parameters) extends LazyModule {
   val node = AHBMasterAdapterNode(

diff --git a/src/main/scala/amba/ahb/Monitor.scala b/src/main/scala/amba/ahb/Monitor.scala
@@ -3,7 +3,6 @@
 package freechips.rocketchip.amba.ahb
 
 import chisel3._
-import freechips.rocketchip.config.Parameters
 
 case class AHBSlaveMonitorArgs(edge: AHBEdgeParameters)
 

diff --git a/src/main/scala/amba/ahb/RegisterRouter.scala b/src/main/scala/amba/ahb/RegisterRouter.scala
@@ -8,7 +8,7 @@ import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
 import freechips.rocketchip.util._
-import scala.math.{min,max}
+import scala.math.min
 
 case class AHBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)(implicit valName: ValName)
   extends SinkNode(AHBImpSlave)(Seq(AHBSlavePortParameters(

diff --git a/src/main/scala/amba/ahb/Xbar.scala b/src/main/scala/amba/ahb/Xbar.scala
@@ -5,9 +5,7 @@ package freechips.rocketchip.amba.ahb
 import Chisel._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.regmapper._
 import freechips.rocketchip.util._
-import scala.math.{min,max}
 
 class AHBFanout()(implicit p: Parameters) extends LazyModule {
   val node = new AHBFanoutNode(

diff --git a/src/main/scala/amba/ahb/package.scala b/src/main/scala/amba/ahb/package.scala
@@ -2,7 +2,6 @@
 
 package freechips.rocketchip.amba
 
-import Chisel._
 import freechips.rocketchip.diplomacy._
 
 package object ahb

diff --git a/src/main/scala/amba/apb/Monitor.scala b/src/main/scala/amba/apb/Monitor.scala
@@ -3,7 +3,6 @@
 package freechips.rocketchip.amba.apb
 
 import chisel3._
-import freechips.rocketchip.config.Parameters
 
 case class APBMonitorArgs(edge: APBEdgeParameters)
 

diff --git a/src/main/scala/amba/apb/RegisterRouter.scala b/src/main/scala/amba/apb/RegisterRouter.scala
@@ -7,8 +7,6 @@ import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
-import freechips.rocketchip.util._
-import scala.math.{min,max}
 
 case class APBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)(implicit valName: ValName)
   extends SinkNode(APBImp)(Seq(APBSlavePortParameters(

diff --git a/src/main/scala/amba/apb/Xbar.scala b/src/main/scala/amba/apb/Xbar.scala
@@ -6,8 +6,6 @@ import Chisel._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
-import freechips.rocketchip.regmapper._
-import scala.math.{min,max}
 
 class APBFanout()(implicit p: Parameters) extends LazyModule {
   val node = new APBNexusNode(

diff --git a/src/main/scala/amba/apb/package.scala b/src/main/scala/amba/apb/package.scala
@@ -2,7 +2,6 @@
 
 package freechips.rocketchip.amba
 
-import Chisel._
 import freechips.rocketchip.diplomacy._
 
 package object apb

diff --git a/src/main/scala/amba/axi4/Buffer.scala b/src/main/scala/amba/axi4/Buffer.scala
@@ -6,7 +6,7 @@ import Chisel._
 import chisel3.util.IrrevocableIO
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
-import scala.math.{min,max}
+import scala.math.min
 
 // pipe is only used if a queue has depth = 1
 class AXI4Buffer(

diff --git a/src/main/scala/amba/axi4/Deinterleaver.scala b/src/main/scala/amba/axi4/Deinterleaver.scala
@@ -3,12 +3,11 @@
 package freechips.rocketchip.amba.axi4
 
 import chisel3._
-import chisel3.util.{Cat, IrrevocableIO, isPow2, log2Ceil,
+import chisel3.util.{Cat, isPow2, log2Ceil,
   log2Up, OHToUInt, Queue, QueueIO, UIntToOH}
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.util.{leftOR, rightOR, UIntToOH1, OH1ToOH}
-import scala.math.{min,max}
+import freechips.rocketchip.util.leftOR
 
 class AXI4Deinterleaver(maxReadBytes: Int, buffer: BufferParams = BufferParams.default)(implicit p: Parameters) extends LazyModule
 {

diff --git a/src/main/scala/amba/axi4/Filter.scala b/src/main/scala/amba/axi4/Filter.scala
@@ -2,7 +2,6 @@
 
 package freechips.rocketchip.amba.axi4
 
-import Chisel._
 import freechips.rocketchip.config._
 import freechips.rocketchip.diplomacy._
 

diff --git a/src/main/scala/amba/axi4/Fragmenter.scala b/src/main/scala/amba/axi4/Fragmenter.scala
@@ -7,7 +7,6 @@ import chisel3.util.IrrevocableIO
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
-import scala.math.{min,max}
 
 case object AXI4FragLast extends ControlKey[Bool]("real_last")
 case class AXI4FragLastField() extends SimpleBundleField(AXI4FragLast)(Output(Bool()), false.B)

diff --git a/src/main/scala/amba/axi4/IdIndexer.scala b/src/main/scala/amba/axi4/IdIndexer.scala
@@ -6,7 +6,6 @@ import Chisel._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
-import scala.math.{min,max}
 
 case object AXI4ExtraId extends ControlKey[UInt]("extra_id")
 case class AXI4ExtraIdField(width: Int) extends SimpleBundleField(AXI4ExtraId)(UInt(OUTPUT, width = width), UInt(0))

diff --git a/src/main/scala/amba/axi4/Monitor.scala b/src/main/scala/amba/axi4/Monitor.scala
@@ -3,7 +3,6 @@
 package freechips.rocketchip.amba.axi4
 
 import chisel3._
-import freechips.rocketchip.config.Parameters
 
 case class AXI4MonitorArgs(edge: AXI4EdgeParameters)
 

diff --git a/src/main/scala/amba/axi4/Protocol.scala b/src/main/scala/amba/axi4/Protocol.scala
@@ -3,7 +3,6 @@
 package freechips.rocketchip.amba.axi4
 
 import Chisel._
-import chisel3.util.{Irrevocable, IrrevocableIO}
 
 object AXI4Parameters
 {

diff --git a/src/main/scala/amba/axi4/RegisterRouter.scala b/src/main/scala/amba/axi4/RegisterRouter.scala
@@ -8,7 +8,6 @@ import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
 import freechips.rocketchip.util._
-import scala.math.{min,max}
 
 case object AXI4RRId extends ControlKey[UInt]("extra_id")
 case class AXI4RRIdField(width: Int) extends SimpleBundleField(AXI4RRId)(UInt(OUTPUT, width = 1 max width), UInt(0))

diff --git a/src/main/scala/amba/axi4/package.scala b/src/main/scala/amba/axi4/package.scala
@@ -2,7 +2,6 @@
 
 package freechips.rocketchip.amba
 
-import Chisel._
 import freechips.rocketchip.diplomacy._
 
 package object axi4

diff --git a/src/main/scala/amba/axis/Buffer.scala b/src/main/scala/amba/axis/Buffer.scala
@@ -2,12 +2,9 @@
 
 package freechips.rocketchip.amba.axis
 
-import chisel3._
-import chisel3.util._
 import freechips.rocketchip.config._
 import freechips.rocketchip.util._
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.tilelink._
 
 class AXISBuffer(val params: BufferParams)(implicit p: Parameters) extends LazyModule
 {

diff --git a/src/main/scala/amba/axis/Nodes.scala b/src/main/scala/amba/axis/Nodes.scala
@@ -2,8 +2,6 @@
 
 package freechips.rocketchip.amba.axis
 
-import chisel3._
-import chisel3.util._
 import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._

diff --git a/src/main/scala/amba/axis/Parameters.scala b/src/main/scala/amba/axis/Parameters.scala
@@ -1,7 +1,6 @@
 // See LICENSE.SiFive for license details.
 package freechips.rocketchip.amba.axis
 
-import chisel3._
 import chisel3.util._
 import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters

diff --git a/src/main/scala/amba/axis/package.scala b/src/main/scala/amba/axis/package.scala
@@ -2,7 +2,6 @@
 
 package freechips.rocketchip.amba
 
-import chisel3._
 import freechips.rocketchip.diplomacy._
 
 package object axis

diff --git a/src/main/scala/devices/debug/APB.scala b/src/main/scala/devices/debug/APB.scala
@@ -1,8 +1,6 @@
 // See LICENSE.SiFive for license details.
 
 package freechips.rocketchip.devices.debug
-import chisel3._
-import chisel3.experimental._
 import freechips.rocketchip.config._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper._

diff --git a/src/main/scala/devices/debug/DMI.scala b/src/main/scala/devices/debug/DMI.scala
@@ -6,7 +6,6 @@ import chisel3._
 import chisel3.util._
 import freechips.rocketchip.config._
 import freechips.rocketchip.util._
-import freechips.rocketchip.util.property._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 

diff --git a/src/main/scala/devices/debug/Debug.scala b/src/main/scala/devices/debug/Debug.scala
@@ -15,11 +15,9 @@ import freechips.rocketchip.tilelink._
 import freechips.rocketchip.devices.tilelink.{DevNullParams, TLError}
 import freechips.rocketchip.interrupts._
 import freechips.rocketchip.util._
-import freechips.rocketchip.util.property._
 import freechips.rocketchip.devices.debug.systembusaccess._
 import freechips.rocketchip.devices.tilelink.TLBusBypass
-import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{DebugLogicalTreeNode, LogicalModuleTree}
-import freechips.rocketchip.diplomaticobjectmodel.model._
+import freechips.rocketchip.diplomaticobjectmodel.logicaltree.DebugLogicalTreeNode
 import freechips.rocketchip.amba.apb.{APBToTL, APBFanout}
 import freechips.rocketchip.util.BooleanToAugmentedBoolean
 
@@ -72,19 +70,16 @@ object DebugModuleAccessType extends scala.Enumeration {
   type DebugModuleAccessType = Value
   val Access8Bit, Access16Bit, Access32Bit, Access64Bit, Access128Bit = Value
 }
-import DebugModuleAccessType._
 
 object DebugAbstractCommandError extends scala.Enumeration {
   type DebugAbstractCommandError = Value
   val Success, ErrBusy, ErrNotSupported, ErrException, ErrHaltResume = Value
 }
-import DebugAbstractCommandError._
 
 object DebugAbstractCommandType extends scala.Enumeration {
   type DebugAbstractCommandType = Value
   val AccessRegister, QuickAccess  = Value
 }
-import DebugAbstractCommandType._
 
 /** Parameters exposed to the top-level design, set based on
   * external requirements, etc.
@@ -762,7 +757,6 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
     import DMI_RegAddrs._
     import DsbRegAddrs._
     import DsbBusConsts._
-    import DMIConsts._
 
     //--------------------------------------------------------------
     // Sanity Check Configuration For this implementation.

diff --git a/src/main/scala/devices/debug/DebugTransport.scala b/src/main/scala/devices/debug/DebugTransport.scala
@@ -9,7 +9,6 @@ import chisel3.experimental.chiselName
 
 import freechips.rocketchip.config._
 import freechips.rocketchip.jtag._
-import freechips.rocketchip.util._
 import freechips.rocketchip.util.property._
 
 

diff --git a/src/main/scala/devices/debug/Periphery.scala b/src/main/scala/devices/debug/Periphery.scala
@@ -8,11 +8,9 @@ import chisel3.util._
 import chisel3.util.HasBlackBoxResource
 import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.subsystem._
-import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.amba.apb._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalModuleTree
-import freechips.rocketchip.diplomaticobjectmodel.model.OMComponent
 import freechips.rocketchip.jtag._
 import freechips.rocketchip.util._
 import freechips.rocketchip.tilelink._

diff --git a/src/main/scala/devices/debug/SBA.scala b/src/main/scala/devices/debug/SBA.scala
@@ -9,15 +9,13 @@ import freechips.rocketchip.config._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.tilelink._
-import freechips.rocketchip.util._
 import freechips.rocketchip.util.property._
 import freechips.rocketchip.devices.debug._
 
 object SystemBusAccessState extends scala.Enumeration {
    type SystemBusAccessState = Value
    val Idle, SBReadRequest, SBWriteRequest, SBReadResponse, SBWriteResponse = Value
-}
-import SystemBusAccessState._ 
+} 
 
 object SBErrorCode extends scala.Enumeration {
   type SBErrorCode = Value
@@ -28,15 +26,13 @@ object SBErrorCode extends scala.Enumeration {
   val BadAccess  = Value(4)
   val OtherError = Value(7)
 }
-import SBErrorCode._
 
 object SystemBusAccessModule
 {
   def apply(sb2tl: SBToTL, dmactive: Bool, dmAuthenticated: Bool)(implicit p: Parameters):
     (Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) =
   {
     import SBErrorCode._
-    import DMI_RegAddrs._
 
     val cfg = p(DebugModuleKey).get
 

diff --git a/src/main/scala/devices/tilelink/BootROM.scala b/src/main/scala/devices/tilelink/BootROM.scala
@@ -4,12 +4,11 @@ package freechips.rocketchip.devices.tilelink
 
 import Chisel._
 import freechips.rocketchip.config.{Field, Parameters}
-import freechips.rocketchip.subsystem.{BaseSubsystem, HierarchicalLocation, HasTiles, TLBusWrapperLocation, CBUS}
+import freechips.rocketchip.subsystem.{BaseSubsystem, HierarchicalLocation, HasTiles, TLBusWrapperLocation}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
-import freechips.rocketchip.util._
 
-import java.nio.{ByteBuffer, ByteOrder}
+import java.nio.ByteBuffer
 import java.nio.file.{Files, Paths}
 
 /** Size, location and contents of the boot rom. */

diff --git a/src/main/scala/devices/tilelink/BusBypass.scala b/src/main/scala/devices/tilelink/BusBypass.scala
@@ -3,12 +3,9 @@
 package freechips.rocketchip.devices.tilelink
 
 import Chisel._
-import chisel3.experimental.withReset
-import freechips.rocketchip.config.{Field, Parameters}
+import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
-import freechips.rocketchip.util._
-import scala.math.min
 
 abstract class TLBusBypassBase(beatBytes: Int, deadlock: Boolean = false, bufferError: Boolean = true, maxAtomic: Int = 16, maxTransfer: Int = 4096)
   (implicit p: Parameters) extends LazyModule

diff --git a/src/main/scala/devices/tilelink/Error.scala b/src/main/scala/devices/tilelink/Error.scala
@@ -6,8 +6,6 @@ import Chisel._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
-import freechips.rocketchip.util._
-import scala.math.min
 
 import freechips.rocketchip.diplomaticobjectmodel.{DiplomaticObjectModelAddressing, HasLogicalTreeNode}
 import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalTreeNode

diff --git a/src/main/scala/devices/tilelink/MaskROM.scala b/src/main/scala/devices/tilelink/MaskROM.scala
@@ -5,7 +5,7 @@ package freechips.rocketchip.devices.tilelink
 import Chisel._
 import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.subsystem.{Attachable, HierarchicalLocation, TLBusWrapperLocation, CBUS}
+import freechips.rocketchip.subsystem.{Attachable, HierarchicalLocation, TLBusWrapperLocation}
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
 

diff --git a/src/main/scala/devices/tilelink/MasterMux.scala b/src/main/scala/devices/tilelink/MasterMux.scala
@@ -3,10 +3,9 @@
 package freechips.rocketchip.devices.tilelink
 
 import Chisel._
-import freechips.rocketchip.config.{Field, Parameters}
+import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
-import freechips.rocketchip.util._
 
 class MasterMuxNode(uFn: Seq[TLMasterPortParameters] => TLMasterPortParameters)(implicit valName: ValName) extends TLCustomNode
 {

diff --git a/src/main/scala/devices/tilelink/TestRAM.scala b/src/main/scala/devices/tilelink/TestRAM.scala
@@ -6,7 +6,6 @@ import Chisel._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
-import freechips.rocketchip.util._
 
 // Do not use this for synthesis! Only for simulation.
 class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, trackCorruption: Boolean = true)(implicit p: Parameters) extends LazyModule

diff --git a/src/main/scala/diplomacy/AddressDecoder.scala b/src/main/scala/diplomacy/AddressDecoder.scala
@@ -3,7 +3,6 @@
 package freechips.rocketchip.diplomacy
 
 import Chisel.log2Ceil
-import scala.math.{max,min}
 
 object AddressDecoder
 {

diff --git a/src/main/scala/diplomacy/AddressRange.scala b/src/main/scala/diplomacy/AddressRange.scala
@@ -2,7 +2,6 @@
 
 package freechips.rocketchip.diplomacy
 
-import Chisel._
 
 // Use AddressSet instead -- this is just for pretty printing
 case class AddressRange(base: BigInt, size: BigInt) extends Ordered[AddressRange]

diff --git a/src/main/scala/diplomacy/BundleBridge.scala b/src/main/scala/diplomacy/BundleBridge.scala
@@ -6,7 +6,7 @@ import chisel3._
 import chisel3.internal.sourceinfo.SourceInfo
 import chisel3.experimental.{DataMirror,IO}
 import chisel3.experimental.DataMirror.internal.chiselTypeClone
-import freechips.rocketchip.config.{Parameters,Field}
+import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.util.DataToAugmentedData
 
 case class BundleBridgeParams[T <: Data](genOpt: Option[() => T])