GitHub - agra-uni-bremen/virtual-bus: Simple protocol to connect two memory mapped buses (e.g. for Hardware In The Loop)

agra-uni-bremen / virtual-bus Public

Simple protocol to connect two memory mapped buses (e.g. for Hardware In The Loop)

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Name		Name	Last commit message	Last commit date
Latest commit History 34 Commits
.gitignore		.gitignore
CMakeLists.txt		CMakeLists.txt
Makefile		Makefile
initiator-cli.cpp		initiator-cli.cpp
initiator.cpp		initiator.cpp
initiator.hpp		initiator.hpp
network_io.cpp		network_io.cpp
network_io.hpp		network_io.hpp
protocol.cpp		protocol.cpp
protocol.hpp		protocol.hpp
responder-cli.cpp		responder-cli.cpp
responder.cpp		responder.cpp
responder.hpp		responder.hpp