Fix bug with typespecs declared in package (chipsalliance#2097)

Co-authored-by: Krzysztof Bieganski <[email protected]>

tests/formal/passlist.txt

@@ -156,6 +156,7 @@ simple:OneReplicate/dut.v
 simple:OneStruct/dut.sv
 simple:OneSysFunc/dut.v
 simple:PackageCast/dut.v
+simple:PackageLogicTypespec/dut.sv
 simple:PackedArray/top.sv
 simple:PackedArrayPort/top.sv
 simple:ParameterColonReference/top.sv

tests/simple_tests/PackageLogicTypespec/Makefile.in

@@ -0,0 +1,2 @@
+TEST_FILES := $(TEST_DIR)/dut.sv
+TOP_MODULE := dut

tests/simple_tests/PackageLogicTypespec/dut.sv

@@ -0,0 +1,9 @@
+package my_pkg;
+
+  typedef logic [31:0] my_type_t;
+
+endpackage
+
+module dut (input wire clk, input my_pkg::my_type_t my_in, output logic [31:0] my_out);
+  assign my_out = my_in;
+endmodule

tests/simple_tests/PackageLogicTypespec/yosys_script.tcl

@@ -0,0 +1,6 @@
+source ../yosys_common.tcl
+
+prep -top \\dut
+write_verilog
+write_verilog yosys.sv
+sim -clock clk -rstlen 10 -vcd dump.vcd