Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Revert "Update AST::process call arguments" #2

Merged
merged 1 commit into from
Apr 24, 2024
Merged

Revert "Update AST::process call arguments" #2

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
19 changes: 1 addition & 18 deletions frontends/systemverilog/compat_symbols.cc
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -8,21 +8,4 @@ YOSYS_NAMESPACE_BEGIN
#include "kernel/constids.inc"
#undef X

#ifdef __linux__
namespace AST
{
extern void process(Design *, AstNode *, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool,
bool, bool, bool);

void __attribute__((weak))
process(RTLIL::Design *design, AST::AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil,
bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool noblackbox, bool lib, bool nowb, bool noopt, bool icells, bool pwires,
bool nooverwrite, bool overwrite, bool defer, bool autowire)
{
process(design, ast, false, dump_ast1, dump_ast2, no_dump_ptr, dump_vlog1, dump_vlog2, dump_rtlil, nolatches, nomeminit, nomem2reg, mem2reg,
noblackbox, lib, nowb, noopt, icells, pwires, nooverwrite, overwrite, defer, autowire);
}

} // namespace AST
#endif
YOSYS_NAMESPACE_END
YOSYS_NAMESPACE_END
37 changes: 6 additions & 31 deletions frontends/systemverilog/uhdm_common_frontend.cc
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -20,20 +20,6 @@
#include "uhdm_common_frontend.h"
#include "synlig_edif.h"

#ifdef __linux__
namespace Yosys
{
using AST::AstNode;
using RTLIL::Design;

namespace AST
{
extern void process(Design *, AstNode *, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool,
bool, bool);
} // namespace AST
} // namespace Yosys
#endif

namespace systemverilog_plugin
{

Expand Down Expand Up @@ -159,27 +145,16 @@ void UhdmCommonFrontend::execute(std::istream *&f, std::string filename, std::ve
AST::set_line_num = &set_line_num;
AST::get_line_num = &get_line_num;

bool dont_redefine = false;
bool default_nettype_wire = true;

AST::AstNode *current_ast = parse(filename);

if (current_ast) {
Yosys::AST::process(design, current_ast, dump_ast1, dump_ast2, no_dump_ptr, dump_vlog1, dump_vlog2, dump_rtlil,
false, // nolatches
false, // nomeminit
false, // nomem2reg
false, // mem2reg
false, // noblackbox
false, // lib
false, // nowb
false, // noopt
false, // icells
false, // pwires
false, // nooverwrite
false, // overwrite
defer, // defer
true // autowire
);
AST::process(design, current_ast, dump_ast1, dump_ast2, no_dump_ptr, dump_vlog1, dump_vlog2, dump_rtlil, false, false, false, false, false,
false, false, false, false, false, dont_redefine, false, defer, default_nettype_wire);
delete current_ast;
}
}

} // namespace systemverilog_plugin
} // namespace systemverilog_plugin
Loading