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projects/ad719x_asdz/coraz7s: Add make parameter and SYNCN on GPIO 33
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 * Made the project parameterizable through IO_PMOD_N parameter
 * Added possibility to connect through the I/O headers as well
 * Separated the top file and the constraints, for I/O headers and for
   PMOD JA
 * Added GPIO 33 - SYNCN, for the Arduino header connection mode (where
   SYNCN is needed). It was hardcoded to 1, because otherwise the core is in
   reset, since this feature is used (when set to 0) for synchronizing
   multiple eval boards, which is not what we want at the moment

Signed-off-by: Iulia Moldovan <[email protected]>
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IuliaCMoldovan committed Oct 31, 2024
1 parent ef0b76b commit f36c2f6
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15 changes: 15 additions & 0 deletions projects/ad719x_asdz/coraz7s/system_constr_io.xdc
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###############################################################################
## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

# coraz7s
# ad719x spi connections

# connect through the I/O header

set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports adc_spi_sclk]; # IO_L19N_T3_VREF_35 Sch=ck_io[13]
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports adc_spi_miso_rdyn]; # IO_L14P_T2_AD4P_SRCC_35 Sch=ck_io[12]
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports adc_spi_mosi]; # IO_L12N_T1_MRCC_35 Sch=ck_io[11]
set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports adc_spi_csn]; # IO_L11N_T1_SRCC_34 Sch=ck_io[10]
set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports adc_syncn]; # IO_L21P_T3_DQS_34 Sch=ck_io[4]
12 changes: 7 additions & 5 deletions ...cts/ad719x_asdz/coraz7s/system_constr.xdc → ...d719x_asdz/coraz7s/system_constr_pmod.xdc
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###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

# coraz7s
# ad719x spi connections

set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33} [get_ports {adc_spi_sclk}]; # IO_L7N_T1_34 Sch=ja_n[2]
set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports {adc_spi_miso_rdyn}]; # IO_L7P_T1_34 Sch=ja_p[2]; AD719X sch=DOUT/RDY_N
set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports {adc_spi_mosi}]; # IO_L17N_T2_34 Sch=ja_n[1]; AD719X sch=DIN
set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports {adc_spi_csn}]; # IO_L17P_T2_34 Sch=ja_p[1]
# connect through the PMOD pins

set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33} [get_ports adc_spi_sclk]; # IO_L7N_T1_34 Sch=ja_n[2]
set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports adc_spi_miso_rdyn]; # IO_L7P_T1_34 Sch=ja_p[2]; AD719X sch=DOUT/RDY_N
set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports adc_spi_mosi]; # IO_L17N_T2_34 Sch=ja_n[1]; AD719X sch=DIN
set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports adc_spi_csn]; # IO_L17P_T2_34 Sch=ja_p[1]
40 changes: 36 additions & 4 deletions projects/ad719x_asdz/coraz7s/system_project.tcl
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###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

# In the case of:
# EVAL-AD7190 and EVAL-AD9175:
# it works both connecting its PMOD to PMOD JA of Cora, and
# placing it on top of Cora, connecting it to the Arduino header
# EVAL-AD7193: only IO_PMOD_N=1;
# works only by placing it on top of Cora, connecting it to the Arduino header

set io_pmod_n 0

# make or make IO_PMOD_N=0 - connect the eval board PMOD to PMOD JA of Cora
# make IO_PMOD_N=1 - connect the eval board to the Arduino header (placing it on top of Cora)

if {[info exists ::env(IO_PMOD_N)]} {
set io_pmod_n $::env(IO_PMOD_N)
} else {
set env(IO_PMOD_N) $io_pmod_n
}

source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl

adi_project ad719x_asdz_coraz7s
adi_project ad719x_asdz_coraz7s 0 [list \
IO_PMOD_N $io_pmod_n \
]

if {$io_pmod_n == "1"} {
# through I/O header
adi_project_files {} [list \
"system_constr_io.xdc" \
"system_top_io.v" \
]
} else {
# PMOD - default mode
adi_project_files {} [list \
"system_constr_pmod.xdc" \
"system_top_pmod.v" \
]
}

adi_project_files ad719x_asdz_coraz7s [list \
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc" \
"system_constr.xdc" \
"system_top.v"
]

adi_project_run ad719x_asdz_coraz7s
162 changes: 162 additions & 0 deletions projects/ad719x_asdz/coraz7s/system_top_io.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module system_top (

inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,

inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,

inout [ 1:0] btn,
inout [ 5:0] led,

// ad7190 spi pins

output adc_spi_sclk,
input adc_spi_miso_rdyn,
output adc_spi_mosi,
output adc_spi_csn,
output adc_syncn
);

// internal signals

wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;

// instantiations

ad_iobuf #(
.DATA_WIDTH (2)
) i_iobuf_buttons (
.dio_t (gpio_t[1:0]),
.dio_i (gpio_o[1:0]),
.dio_o (gpio_i[1:0]),
.dio_p (btn));

ad_iobuf #(
.DATA_WIDTH (6)
) i_iobuf_leds (
.dio_t (gpio_t[7:2]),
.dio_i (gpio_o[7:2]),
.dio_o (gpio_i[7:2]),
.dio_p (led));

// hardcoded to 1 so the core won't be in reset, since we don't support
// synchronization across multiple devices (where SYNCN is needed); check
// data sheet for more details
assign adc_syncn = 1'b1;

// project specific gpios

assign gpio_i[63:34] = gpio_o[63:34];
assign gpio_i[32] = adc_spi_miso_rdyn;
assign gpio_i[33] = adc_syncn;

// board specific gpios

assign gpio_i[31:8] = gpio_o[31:8];

system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),

.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),

.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),

.spi0_clk_i (1'b0),
.spi0_clk_o (adc_spi_sclk),
.spi0_csn_0_o (adc_spi_csn),
.spi0_csn_1_o (),
.spi0_csn_2_o (),
.spi0_csn_i (1'b0),
.spi0_sdi_i (adc_spi_miso_rdyn),
.spi0_sdo_i (1'b0),
.spi0_sdo_o (adc_spi_mosi),

.spi1_clk_i (1'b0),
.spi1_clk_o (),
.spi1_csn_0_o (),
.spi1_csn_1_o (),
.spi1_csn_2_o (),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b0),
.spi1_sdo_i (1'b0),
.spi1_sdo_o ());

endmodule
2 changes: 1 addition & 1 deletion projects/ad719x_asdz/coraz7s/system_top.v → ...cts/ad719x_asdz/coraz7s/system_top_pmod.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
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