AD7616: Add AXI ADC support #1477

PIoandan · 2024-10-01T07:22:10Z

PR Description

Add AXI ADC support to existing AD7616 PIF project.
Update AD7616 project to account for the changes (add CPACK core, fix DMA connections).
Update AXI_AD7616 and AD7616 (project) documentation and block diagrams

PR Type

Bug fix (change that fixes an issue)
New feature (change that adds new functionality)
Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

I have followed the code style guidelines
I have performed a self-review of changes
I have compiled all hdl projects and libraries affected by this PR
I have tested in hardware affected projects, at least on relevant boards
I have commented my code, at least hard-to-understand parts
I have signed off all commits from this PR
I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
I have not introduced new Warnings/Critical Warnings on compilation
I have added new hdl testbenches or updated existing ones

sarpadi · 2024-11-27T13:14:36Z

library/axi_ad7616/axi_ad7616_pif.v

@@ -67,7 +82,7 @@ module axi_ad7616_pif #(
  input                   rd_req,
  input                   wr_req,
  input       [15:0]      wr_data,
-  output  reg [15:0]      rd_data,
+  output  reg [15:0]      rd_data = 'ha1b2,


Remove / fix initialization

sarpadi · 2024-11-27T13:15:26Z

library/axi_ad7616/axi_ad7616_pif.v

@@ -96,10 +111,20 @@ module axi_ad7616_pif #(

  reg                             rd_valid_d = 1'h0;

+  reg     [ 4:0]                  channel_counter = 5'h0;


fix spacing, separate reg from wire reclarations, initializations

sarpadi · 2024-11-27T13:15:52Z

library/axi_ad7616/axi_ad7616_pif.v

+    rd_req_edge_d <= rd_req_edge;
+  end
+
+  //channel_counter


irrelevant comment. delete or elaborate

sarpadi · 2024-11-27T13:34:53Z

library/axi_ad7616/axi_ad7616.v

+
+  wire [255:0] adc_data_s;
+
+  wire [ 7:0]           adc_custom_control;


spacing cleanup

sarpadi · 2024-11-27T13:36:18Z

library/axi_ad7616/axi_ad7616.v

+    end
+  endgenerate
+
+      axi_ad7616_pif #(


fix indentation

sarpadi · 2024-11-27T13:36:35Z

library/axi_ad7616/axi_ad7616.v

+  assign adc_data_1 = dma_data[14*16+15:14*16];
+  assign adc_data_0 = dma_data[15*16+15:15*16];
+
+  wire [31:0] adc_config_ctrl;


move declaration

sarpadi · 2024-11-27T13:40:32Z

Update system_project.tcl with newer build parameter handling

sarpadi · 2024-11-27T13:40:37Z

fix conflicts

sarpadi · 2024-11-27T13:42:16Z

projects/ad7616_sdz/common/ad7616_bd.tcl

remove 100MHz clock gen core and use PS clk (sys_clk) instead

PIoandan · 2024-11-28T14:55:58Z

Made a squash for all three categories of files.

IuliaCMoldovan · 2024-12-04T05:52:16Z

docs/library/axi_ad7616/index.rst

@@ -9,7 +9,8 @@ The :git-hdl:`AXI AD7616 <library/axi_ad7616>` IP core
 can be used to interface the :adi:`AD7616` device using an
 FPGA. The core has a AXI Memory Map interface for configuration, supports the
 parallel data interface of the device, and has a simple FIFO interface for the
-DMAC.
+DMAC. More about the generic framework interfacing ADCs, that contains the


Suggested change

DMAC. More about the generic framework interfacing ADCs, that contains the

DMAC.

More about the generic framework interfacing ADCs, that contains the

IuliaCMoldovan · 2024-12-04T05:53:42Z

docs/library/axi_ad7616/index.rst

+module, is used in this way: bit 1 - RD request to the device register map('b1),
+bit 0 - WR request to the device register map('b1). Also, **adc_custom_control**
+signal, that is available in the *up_adc_common* module, controls burst_length.
+


Suggested change

IuliaCMoldovan · 2024-12-04T05:53:48Z

docs/library/axi_ad7616/index.rst

+  ['tspan', 'CHx CONVERSION START']
+      }
+   }
+


Suggested change

IuliaCMoldovan · 2024-12-04T05:56:45Z

projects/ad7616_sdz/zed/Makefile

@@ -31,5 +31,6 @@ LIB_DEPS += spi_engine/spi_engine_interconnect
 LIB_DEPS += spi_engine/spi_engine_offload


axi_clkgen should be removed from here as well

This is still needed because in the design we have axi_hdmi_clkgen.

IuliaCMoldovan · 2024-12-04T05:58:48Z

docs/projects/ad7616_sdz/index.rst

-     - :ref:`axi_sysid`
+     - :ref:`here <axi_sysid>`
+   * - UTIL_CPACK2
+     - :git-hdl:`library/util_pack/util_cpack2 <library/util_pack/util_cpack2>` *


Suggested change

- :git-hdl:`library/util_pack/util_cpack2 <library/util_pack/util_cpack2>` *

- :git-hdl:`library/util_pack/util_cpack2` *

IuliaCMoldovan · 2024-12-04T08:10:41Z

library/axi_ad7616/axi_ad7616.v

+    up_rdata_r = 'h00;
+    up_rack_r = 'h00;
+    up_wack_r = 'h00;
+    for (j = 0; j <= 16; j=j+1) begin


< 16 and not <= 16, right?

Suggested change

for (j = 0; j <= 16; j=j+1) begin

for (j = 0; j < 16; j = j + 1) begin

<= 16 : https://github.com/analogdevicesinc/hdl/blob/dev_axi_ad7616/library/axi_ad7616/axi_ad7616.v#L438

IuliaCMoldovan · 2024-12-04T08:12:35Z

library/axi_ad7616/axi_ad7616_ip.tcl

+    "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
+    "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
+    "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
+    "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
    "axi_ad7616_pif.v" \
    "axi_ad7616.v" ]

 adi_ip_properties axi_ad7616

 set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad7616} [ipx::current_core]


Replace the link with https://analogdevicesinc.github.io/hdl/library/axi_ad7616/index.html

Signed-off-by: Pop Ioan Daniel <[email protected]>

PIoandan requested review from IuliaCMoldovan, gastmaier, StancaPop, LBFFilho, alin724 and ladace as code owners October 1, 2024 07:22

PIoandan marked this pull request as draft October 1, 2024 07:23

PIoandan added enhancement doc labels Oct 1, 2024

PIoandan force-pushed the dev_axi_ad7616 branch from cfd86f8 to 365cdd3 Compare October 4, 2024 12:48

sarpadi reviewed Nov 27, 2024

View reviewed changes

PIoandan force-pushed the dev_axi_ad7616 branch 3 times, most recently from 5711fcc to 14394f4 Compare November 28, 2024 12:18

PIoandan marked this pull request as ready for review November 28, 2024 12:20

PIoandan requested a review from sarpadi November 28, 2024 12:20

PIoandan force-pushed the dev_axi_ad7616 branch from 1219f33 to 63b6c32 Compare November 28, 2024 14:51

IuliaCMoldovan requested changes Dec 4, 2024

View reviewed changes

PIoandan force-pushed the dev_axi_ad7616 branch from 63b6c32 to a0f3023 Compare December 4, 2024 11:22

PIoandan added 3 commits December 4, 2024 13:29

library: axi_ad7616: Add AXI ADC

4d2fd5a

Signed-off-by: Pop Ioan Daniel <[email protected]>

projects: ad7616: Project development

d1aa08a

Signed-off-by: Pop Ioan Daniel <[email protected]>

docs: Update ad7616 documentation

67a9226

Signed-off-by: Pop Ioan Daniel <[email protected]>

PIoandan force-pushed the dev_axi_ad7616 branch from 6710f8b to 67a9226 Compare December 4, 2024 11:31

PIoandan requested a review from IuliaCMoldovan December 4, 2024 11:43

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AD7616: Add AXI ADC support #1477

AD7616: Add AXI ADC support #1477

PIoandan commented Oct 1, 2024 •

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		@@ -96,10 +111,20 @@ module axi_ad7616_pif #(

		reg rd_valid_d = 1'h0;

		reg [ 4:0] channel_counter = 5'h0;

		@@ -31,5 +31,6 @@ LIB_DEPS += spi_engine/spi_engine_interconnect
		LIB_DEPS += spi_engine/spi_engine_offload

	- :git-hdl:`library/util_pack/util_cpack2 <library/util_pack/util_cpack2>` *
	- :git-hdl:`library/util_pack/util_cpack2` *

	for (j = 0; j <= 16; j=j+1) begin
	for (j = 0; j < 16; j = j + 1) begin

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PIoandan commented Oct 1, 2024 • edited Loading

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sarpadi commented Nov 27, 2024

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PIoandan commented Oct 1, 2024 •

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