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[SOL] Create explicit sign extension instruction #114

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LucasSte
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As described in solana-foundation/solana-improvement-documents#174, mov32 reg, reg will now serve for sign extension.

The changes in this PR are the following:

  1. Use mov64 for copying 32-bit registers.
  2. Use mov32 reg, reg for sign extension.
  3. Use mov64 reg, reg for zero extension. I'm assuming I'll always keep the high bits clear in 32-bit sub-registers.
  4. Use and32 reg, -1 for truncation.

I haven't done yet an integration test in the VM, because jump instructions do not work with ALU32. I'll fix that in a following PR and work on the necessary tests.

@LucasSte LucasSte requested a review from dmakarov November 25, 2024 20:28
@LucasSte LucasSte marked this pull request as ready for review November 25, 2024 20:28
@dmakarov
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dmakarov commented Dec 2, 2024

looks good, except for minor naming inconsistencies. If you have setHasExplicitSext (which I think should be setHasExplicitSignExt), maybe the getter should also be getHasExplicitSignExt, instead of getExplicitSignExt.

@LucasSte LucasSte force-pushed the explicit-sign-ext-instr branch from 74c6d84 to fe185ba Compare December 2, 2024 21:42
llvm/lib/Target/SBF/SBFInstrInfo.h Outdated Show resolved Hide resolved
@LucasSte LucasSte merged commit f602770 into anza-xyz:solana-rustc/18.1-2024-05-19 Dec 3, 2024
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@LucasSte LucasSte deleted the explicit-sign-ext-instr branch December 3, 2024 15:03
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2 participants