nxstyle fix

Signed-off-by: Peter Bee <[email protected]>

Documentation/platforms/arm/rp23xx/boards/raspberrypi-pico-2/README.txt

@@ -1,7 +1,7 @@
 README
 ======
 
-This directory contains the port of NuttX to the Raspberry Pi Pico.
+This directory contains the port of NuttX to the Raspberry Pi Pico 2.
 See https://www.raspberrypi.org/products/raspberry-pi-pico-2/ for information
 about Raspberry Pi Pico 2.
 
@@ -24,7 +24,7 @@ Installation
   $ cd nuttx
   $ make distclean
   $ ./tools/configure.sh raspberrypi-pico-2:nsh
-  $ make V=1
+  $ make -j
 
 4. Connect Raspberry Pi Pico 2 board to USB port while pressing BOOTSEL.
    The board will be detected as USB Mass Storage Device.
@@ -46,18 +46,3 @@ Defconfigs
 
 - usbnsh
     USB CDC/ACM serial console with NuttShell
-
-License exceptions
-==================
-
-The following files are originated from the files in Pico SDK.
-So, the files are licensed under 3-Clause BSD same as Pico SDK.
-
-- arch/arm/src/rp23xx/rp23xx_clock.c
-- arch/arm/src/rp23xx/rp23xx_pll.c
-- arch/arm/src/rp23xx/rp23xx_xosc.c
-  - These are created by referring the Pico SDK clock initialization.
-
-- arch/arm/src/rp23xx/hardware/*.h
-- arch/arm/src/rp23xx/pico/*.h
-  - These are originally provided in Pico SDK.

Documentation/platforms/arm/rp23xx/boards/raspberrypi-pico-2/index.rst

@@ -1,5 +1,5 @@
 ===============================
-Raspberry Pi Pico
+Raspberry Pi Pico 2
 ===============================
 
 The `Raspberry Pi Pico 2 <https://www.raspberrypi.com/products/raspberry-pi-pico-2/>`_ is a general purpose board supplied by

arch/arm/src/rp23xx/hardware/rp23xx_dma.h

@@ -33,7 +33,6 @@
 
 /* Register offsets *********************************************************/
 
-
 #define RP23XX_DMA_READ_ADDR_OFFSET                  0x000000  /* DMA Read Address pointer */
 #define RP23XX_DMA_WRITE_ADDR_OFFSET                 0x000004  /* DMA Write Address pointer */
 #define RP23XX_DMA_TRANS_COUNT_OFFSET                0x000008  /* DMA Transfer Count */
@@ -240,4 +239,4 @@
 #define RP23XX_DMA_SECCFG_MISC_TIMER3_S                    (1 << 9)
 #define RP23XX_DMA_DBG_CTDREQ_MASK                         (0x3f)
 
-#endif /*__ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_DMA_H*/
+#endif /* __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_DMA_H */

arch/arm/src/rp23xx/hardware/rp23xx_pio.h

@@ -98,9 +98,9 @@
 #define RP23XX_PIO_CTRL_NEXTPREV_CLKDIV_RESTART     (1 << 26)  /* Write 1 to restart the clock dividers of state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to writing 1 to the corresponding CLKDIV_RESTART bits in those PIOs' CTRL registers */
 #define RP23XX_PIO_CTRL_NEXTPREV_SM_DISABLE         (1 << 25)  /* Write 1 to disable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to clearing the corresponding SM_ENABLE bits in those PIOs' CTRL registers */
 #define RP23XX_PIO_CTRL_NEXTPREV_SM_ENABLE          (1 << 24)  /* Write 1 to enable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to clearing the corresponding SM_ENABLE bits in those PIOs' CTRL registers. If both OTHERS_SM_ENABLE and OTHERS_SM_DISABLE are set, the disable takes precedence */
-#define RP23XX_PIO_NEXT_PIO_MASK_SHIFT              (20)    /* A mask of state machines in the neighbouring highernumbered PIO block in the system (or PIO block 0 if this is the highestnumbered PIO block) to which to apply the operations specified by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and NEXTPREV_SM_DISABLE in the same write */
+#define RP23XX_PIO_NEXT_PIO_MASK_SHIFT              (20)       /* A mask of state machines in the neighbouring highernumbered PIO block in the system (or PIO block 0 if this is the highestnumbered PIO block) to which to apply the operations specified by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and NEXTPREV_SM_DISABLE in the same write */
 #define RP23XX_PIO_NEXT_PIO_MASK_MASK               (0xf)
-#define RP23XX_PIO_PREV_PIO_MASK_SHIFT              (16)    /* A mask of state machines in the neighbouring lowernumbered PIO block in the system (or the highest-numbered PIO block if this is PIO block 0) to which to apply the operations specified by OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same write */
+#define RP23XX_PIO_PREV_PIO_MASK_SHIFT              (16)       /* A mask of state machines in the neighbouring lowernumbered PIO block in the system (or the highest-numbered PIO block if this is PIO block 0) to which to apply the operations specified by OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same write */
 #define RP23XX_PIO_PREV_PIO_MASK_MASK               (0xf)
 
 #define RP23XX_PIO_CTRL_CLKDIV_RESTART_SHIFT        (8)     /* Force clock dividers to restart their count and clear fractional accumulators. Restart multiple dividers to synchronise them. */

arch/arm/src/rp23xx/hardware/rp23xx_sha256.h

@@ -55,5 +55,4 @@
 #define RP23XX_SHA256_WDATA_MASK             (0xffffffff)
 #define RP23XX_SHA256_SUM_MASK               (0xffffffff)
 
-
 #endif /* __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_SHA256_H */

arch/arm/src/rp23xx/rp23xx_gpio.c

@@ -107,7 +107,7 @@ static const int g_gpio_function_mapping_i2c[2][9] =
   {
     0,  4,  8, 12, 16, 20, 24, 28,
 #ifdef CONFIG_RP23XX_RP2350B
-32, 36, 40, 44,
+    32, 36, 40, 44,
 #endif
     -1
   }, /* pin numbers assignable to I2C0 */
@@ -293,7 +293,7 @@ void rp23xx_gpio_set_function(uint32_t gpio, uint32_t func)
 
   modbits_reg32(RP23XX_PADS_BANK0_GPIO_IE,
                 RP23XX_PADS_BANK0_GPIO_ISO |
-                RP23XX_PADS_BANK0_GPIO_IE | 
+                RP23XX_PADS_BANK0_GPIO_IE |
                 RP23XX_PADS_BANK0_GPIO_OD,
                 RP23XX_PADS_BANK0_GPIO(gpio));
 

arch/arm/src/rp23xx/rp23xx_heaps.c

@@ -36,7 +36,7 @@
  ****************************************************************************/
 
 static void * const psram_start = (void *)0x11000000ul;
-static const size_t psram_size = 8*1024*1024;
+static const size_t psram_size = 8 * 1024 * 1024;
 
 /****************************************************************************
  * Public Functions
@@ -51,7 +51,7 @@ static struct mm_heap_s *g_psramheap;
 #error cannot use CONFIG_MM_KERNEL_HEAP with single heap
 #endif
 
-#if CONFIG_MM_REGIONS > 1 
+#if CONFIG_MM_REGIONS > 1
 void arm_addregion(void)
 {
   /* Add the PSRAM region to main heap */
@@ -68,7 +68,8 @@ void arm_addregion(void)
 
 /* Use the internal SRAM as the kernel heap */
 
-void up_allocate_kheap(void **heap_start, size_t *heap_size) {
+void up_allocate_kheap(void **heap_start, size_t *heap_size)
+{
   *heap_start = (void *)g_idle_topstack;
 
 #ifdef CONFIG_ARCH_PGPOOL_PBASE
@@ -78,9 +79,10 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size) {
 #endif
 }
 
-/* Use the external PSRAM as the default user heap*/
+/* Use the external PSRAM as the default user heap */
 
-void up_allocate_heap(void **heap_start, size_t *heap_size) {
+void up_allocate_heap(void **heap_start, size_t *heap_size)
+{
   *heap_start = psram_start;
   *heap_size = psram_size;
 }

arch/arm/src/rp23xx/rp23xx_irq.c

@@ -108,14 +108,20 @@ static void rp23xx_dumpnvic(const char *msg, int irq)
           getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
           getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
   irqinfo("              %08x %08x %08x %08x\n",
-          getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
-          getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
+          getreg32(NVIC_IRQ16_19_PRIORITY),
+          getreg32(NVIC_IRQ20_23_PRIORITY),
+          getreg32(NVIC_IRQ24_27_PRIORITY),
+          getreg32(NVIC_IRQ28_31_PRIORITY));
   irqinfo("              %08x %08x %08x %08x\n",
-          getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
-          getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
+          getreg32(NVIC_IRQ32_35_PRIORITY),
+          getreg32(NVIC_IRQ36_39_PRIORITY),
+          getreg32(NVIC_IRQ40_43_PRIORITY),
+          getreg32(NVIC_IRQ44_47_PRIORITY));
   irqinfo("              %08x %08x %08x %08x\n",
-          getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
-          getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
+          getreg32(NVIC_IRQ48_51_PRIORITY),
+          getreg32(NVIC_IRQ52_55_PRIORITY),
+          getreg32(NVIC_IRQ56_59_PRIORITY),
+          getreg32(NVIC_IRQ60_63_PRIORITY));
 
   irqinfo("SYSCON:\n");
   irqinfo("  CPUID:      %08x\n",
@@ -203,7 +209,8 @@ static inline void rp23xx_clrpend(int irq)
         }
       else
         {
-          putreg32((1 << (irq - RP23XX_IRQ_EXTINT - 32)), NVIC_IRQ32_63_CLRPEND);
+          putreg32((1 << (irq - RP23XX_IRQ_EXTINT - 32)),
+                   NVIC_IRQ32_63_CLRPEND);
         }
     }
 }
@@ -321,7 +328,8 @@ void up_disable_irq(int irq)
         }
       else
         {
-          putreg32((1 << (irq - RP23XX_IRQ_EXTINT - 32)), NVIC_IRQ32_63_CLEAR);
+          putreg32((1 << (irq - RP23XX_IRQ_EXTINT - 32)),
+                   NVIC_IRQ32_63_CLEAR);
         }
     }
 
@@ -376,7 +384,8 @@ void up_enable_irq(int irq)
         }
       else
         {
-          putreg32((1 << (irq - RP23XX_IRQ_EXTINT - 32)), NVIC_IRQ32_63_ENABLE);      
+          putreg32((1 << (irq - RP23XX_IRQ_EXTINT - 32)),
+                   NVIC_IRQ32_63_ENABLE);
         }
     }
 

arch/arm/src/rp23xx/rp23xx_pio_instructions.h

@@ -1,6 +1,6 @@
 /****************************************************************************
  * arch/arm/src/rp23xx/rp23xx_pio_instructions.h
- * 
+ *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with
  * this work for additional information regarding copyright ownership.  The
@@ -294,8 +294,9 @@ inline static uint32_t pio_encode_irq_set(bool relative, uint32_t irq)
                                     _pio_encode_irq(relative, irq));
 }
 
-inline static uint32_t pio_encode_irq_wait(bool relative, uint32_t irq) {
-    return _pio_encode_instr_and_args(pio_instr_bits_irq, 1, 
+inline static uint32_t pio_encode_irq_wait(bool relative, uint32_t irq)
+{
+    return _pio_encode_instr_and_args(pio_instr_bits_irq, 1,
                                       _pio_encode_irq(relative, irq));
 }
 

arch/arm/src/rp23xx/rp23xx_rom.h

@@ -29,9 +29,9 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-// ROM FUNCTIONS
+/* ROM FUNCTIONS */
 
-// RP2040 & RP2350
+/* RP2040 & RP2350 */
 #define ROM_DATA_SOFTWARE_GIT_REVISION          ROM_TABLE_CODE('G', 'R')
 #define ROM_FUNC_FLASH_ENTER_CMD_XIP            ROM_TABLE_CODE('C', 'X')
 #define ROM_FUNC_FLASH_EXIT_XIP                 ROM_TABLE_CODE('E', 'X')
@@ -40,7 +40,7 @@
 #define ROM_FUNC_FLASH_RANGE_ERASE              ROM_TABLE_CODE('R', 'E')
 #define ROM_FUNC_FLASH_RANGE_PROGRAM            ROM_TABLE_CODE('R', 'P')
 
-// RP2350 only
+/* RP2350 only */
 #define ROM_FUNC_PICK_AB_PARTITION              ROM_TABLE_CODE('A', 'B')
 #define ROM_FUNC_CHAIN_IMAGE                    ROM_TABLE_CODE('C', 'I')
 #define ROM_FUNC_EXPLICIT_BUY                   ROM_TABLE_CODE('E', 'B')
@@ -65,15 +65,15 @@
 #define ROM_FUNC_FLASH_SELECT_XIP_READ_MODE     ROM_TABLE_CODE('X', 'M')
 #define ROM_FUNC_VALIDATE_NS_BUFFER             ROM_TABLE_CODE('V', 'B')
 
-// these form a bit set
+/* these form a bit set */
 #define BOOTROM_STATE_RESET_CURRENT_CORE 0x01
 #define BOOTROM_STATE_RESET_OTHER_CORE   0x02
-#define BOOTROM_STATE_RESET_GLOBAL_STATE 0x04 // reset any global state (e.g. permissions)
+#define BOOTROM_STATE_RESET_GLOBAL_STATE 0x04 /* reset any global state (e.g. permissions) */
 
 #define RT_FLAG_FUNC_RISCV      0x0001
 #define RT_FLAG_FUNC_RISCV_FAR  0x0003
 #define RT_FLAG_FUNC_ARM_SEC    0x0004
-// reserved for 32-bit pointer: 0x0008
+/* reserved for 32-bit pointer: 0x0008 */
 #define RT_FLAG_FUNC_ARM_NONSEC 0x0010
 
 #define BOOTROM_FUNC_TABLE_OFFSET 0x14
@@ -90,15 +90,6 @@
 #define BOOTROM_TABLE_LOOKUP_OFFSET     (BOOTROM_FUNC_TABLE_OFFSET + BOOTROM_WELL_KNOWN_PTR_SIZE)
 #endif
 
-/*! \brief Return a bootrom lookup code based on two ASCII characters
- * \ingroup pico_bootrom
- *
- * These codes are uses to lookup data or function addresses in the bootrom
- *
- * \param c1 the first character
- * \param c2 the second character
- * \return the 'code' to use in rom_func_lookup() or rom_data_lookup()
- */
 #define ROM_TABLE_CODE(c1, c2) ((c1) | ((c2) << 8))
 
 /****************************************************************************
@@ -107,20 +98,31 @@
 
 typedef void *(*rom_table_lookup_fn)(uint32_t code, uint32_t mask);
 
-static __inline void *rom_func_lookup(uint32_t code) {
+static __inline void *rom_func_lookup(uint32_t code)
+{
 #ifdef __riscv
-    uint32_t rom_offset_adjust = rom_size_is_64k() ? 32 * 1024 : 0;
-    // on RISC-V the code (a jmp) is actually embedded in the table
-    rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) (uintptr_t)*(uint16_t*)(BOOTROM_TABLE_LOOKUP_ENTRY_OFFSET + rom_offset_adjust);
-    return rom_table_lookup(code, RT_FLAG_FUNC_RISCV);
+  uint32_t rom_offset_adjust = rom_size_is_64k() ? 32 * 1024 : 0;
+
+  /* on RISC-V the code (a jmp) is actually embedded in the table */
+
+  rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) (uintptr_t)
+    *(uint16_t *)(BOOTROM_TABLE_LOOKUP_ENTRY_OFFSET + rom_offset_adjust);
+
+  return rom_table_lookup(code, RT_FLAG_FUNC_RISCV);
 #else
-    // on ARM the function pointer is stored in the table, so we dereference it
-    // via lookup() rather than lookup_entry()
-    rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) (uintptr_t)*(uint16_t*)(BOOTROM_TABLE_LOOKUP_OFFSET);
-    if (pico_processor_state_is_nonsecure()) {
-        return rom_table_lookup(code, RT_FLAG_FUNC_ARM_NONSEC);
-    } else {
-        return rom_table_lookup(code, RT_FLAG_FUNC_ARM_SEC);
+  /* on ARM the function pointer is stored in the table, so we dereference
+   * it via lookup() rather than lookup_entry()
+   */
+
+  rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) (uintptr_t)
+    *(uint16_t *)(BOOTROM_TABLE_LOOKUP_OFFSET);
+  if (pico_processor_state_is_nonsecure())
+    {
+      return rom_table_lookup(code, RT_FLAG_FUNC_ARM_NONSEC);
+    }
+  else
+    {
+      return rom_table_lookup(code, RT_FLAG_FUNC_ARM_SEC);
     }
 #endif
 }

arch/arm/src/rp23xx/rp23xx_serial.c

@@ -1036,7 +1036,6 @@ void up_putc(int ch)
 #ifdef HAVE_CONSOLE
   up_restoreuartint(priv, ier);
 #endif
-
 }
 
 #else /* USE_SERIALDRIVER */

arch/arm/src/rp23xx/rp23xx_smpcall.c

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/rp23xx/rp23xx_cpupause.c
+ * arch/arm/src/rp23xx/rp23xx_smpcall.c
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with