follow upstream change & fix minor things

Signed-off-by: Peter Bee <[email protected]>

Documentation/platforms/arm/rp23xx/boards/raspberrypi-pico-2/README.txt

@@ -1,11 +1,11 @@
 README
 ======
 
-This directory contains the port of NuttX to the Raspberry Pi Pico.
+This directory contains the porting of NuttX to the Raspberry Pi Pico 2.
 See https://www.raspberrypi.org/products/raspberry-pi-pico-2/ for information
 about Raspberry Pi Pico 2.
 
-NuttX supports the following RP2530 capabilities:
+NuttX supports the following RP2350 capabilities:
   - UART  (console port)
     - GPIO 0 (UART0 TX) and GPIO 1 (UART0 RX) are used for the console.
   - ADC
@@ -24,18 +24,18 @@ Installation
   $ cd nuttx
   $ make distclean
   $ ./tools/configure.sh raspberrypi-pico-2:nsh
-  $ make V=1
+  $ make -j
 
-4. Connect Raspberry Pi Pico 2 board to USB port while pressing BOOTSEL.
+4. Connect Raspberry Pi Pico 2 board to the USB port while pressing BOOTSEL.
    The board will be detected as USB Mass Storage Device.
    Then copy "nuttx.uf2" into the device.
    (Same manner as the standard Pico SDK applications installation.)
 
 5. To access the console, GPIO 0 and 1 pins must be connected to the
-   device such as USB-serial converter.
+   device such as a USB-serial converter.
 
    `usbnsh` configuration provides the console access by USB CDC/ACM serial
-   devcice.  The console is available by using a terminal software on the USB
+   device. The console is available by using a terminal software on the USB
    host.
 
 Defconfigs
@@ -46,18 +46,3 @@ Defconfigs
 
 - usbnsh
     USB CDC/ACM serial console with NuttShell
-
-License exceptions
-==================
-
-The following files are originated from the files in Pico SDK.
-So, the files are licensed under 3-Clause BSD same as Pico SDK.
-
-- arch/arm/src/rp23xx/rp23xx_clock.c
-- arch/arm/src/rp23xx/rp23xx_pll.c
-- arch/arm/src/rp23xx/rp23xx_xosc.c
-  - These are created by referring the Pico SDK clock initialization.
-
-- arch/arm/src/rp23xx/hardware/*.h
-- arch/arm/src/rp23xx/pico/*.h
-  - These are originally provided in Pico SDK.

Documentation/platforms/arm/rp23xx/boards/raspberrypi-pico-2/index.rst

@@ -1,5 +1,5 @@
 ===============================
-Raspberry Pi Pico
+Raspberry Pi Pico 2
 ===============================
 
 The `Raspberry Pi Pico 2 <https://www.raspberrypi.com/products/raspberry-pi-pico-2/>`_ is a general purpose board supplied by
@@ -23,7 +23,7 @@ Features
 * Accurate clock and timer on-chip
 * Temperature sensor
 * Accelerated floating point libraries on-chip
-* 8 × Programmable IO (PIO) state machines for custom peripheral support
+* 12 × Programmable IO (PIO) state machines for custom peripheral support
 
 Serial Console
 ==============
@@ -41,9 +41,9 @@ User LED controlled by GPIO25 and is configured as autoled by default.
 
 A BOOTSEL button, which if held down when power is first
 applied to the board, will cause the RP2350 to boot into programming
-mode and appear as a storage device to a computer connected via USB .
+mode and appear as a storage device to the computer connected via USB.
 Saving a .UF2 file to this device will replace the Flash ROM contents
-on the RP2040.
+on the RP2350.
 
 Pin Mapping
 ===========

Documentation/platforms/arm/rp23xx/index.rst

@@ -16,32 +16,32 @@ Most drivers were copied from the rp2040 port with some modifications.
 
 The following list indicates peripherals currently supported in NuttX:
 
-==============   ======        =====
+==============   ============  =====
 Peripheral       Status        Notes
-==============   ======        =====
+==============   ============  =====
 GPIO             Working       See Supported Boards documentation for available pins.
 UART             Working       GPIO 0 (UART0 TX) and GPIO 1 (UART0 RX) are used for the console.
 I2C              Untested
-SPI Master       Untested
-SPI Slave        Not working
+SPI Master       Working
+SPI Slave        Untested
 DMAC             Untested
 PWM              Untested
 USB              Experimental  usbnsh configuration is somewhat working with some data corruption
-PIO              Untested
+PIO              Working
 IRQs             Working
 DMA              Untested
 Clock Output     Untested
 Flash ROM Boot   Working       Does not require boot2 from pico-sdk
                                If picotool is available a nuttx.uf2 file will be created
 SRAM Boot        Working       Requires external SWD debugger
 PSRAM            Working       Three modes of heap allocation described below
-==============   ======        =====
+==============   ============  =====
 
 Installation
 ============
 
 1. Download and build picotool, make it available in the PATH::
-   
+
     git clone https://github.com/raspberrypi/picotool.git picotool
     cd picotool
     mkdir build
@@ -52,7 +52,7 @@ Installation
 
 2. Download NuttX and the companion applications.  These must both be
    contained in the same directory::
-  
+
     git clone https://github.com/apache/nuttx.git nuttx
     git clone https://github.com/apache/nuttx-apps.git apps
 
@@ -78,7 +78,7 @@ Building NuttX
     make menuconfig
 
 5. Build NuttX::
- 
+
     make
 
 Flash boot
@@ -94,14 +94,14 @@ the flash on startup).
 
 It is also possible to execute from SRAM, which reduces the
 available SRAM to the OS and applications, however it is very
-useful when debugging as erasings and rewriting the flash on
+useful when debugging as erasing and rewriting the flash on
 every build is tedious and slow. This option is enabled with
 `BOOT_RUNFROMISRAM` and requires `openocd`` and/or `gdb`.
 
 There is a third option which is to write the firmware on the
 flash and it gets copied to the SRAM. This is enabled with
 `CONFIG_BOOT_COPYTORAM` and might be useful for time critical
-applications, on the expense of reduced useable interna SRAM
+applications, on the expense of reduced usable internal SRAM
 memory.
 
 PSRAM
@@ -195,7 +195,7 @@ Most builds provide access to the console via UART0.  To access this
 GPIO 0 and 1 pins must be connected to the device such as USB-serial converter.
 
 The `usbnsh` configuration provides the console access by USB CDC/ACM serial
-devcice.  The console is available by using a terminal software on the USB host.
+device.  The console is available by using a terminal software on the USB host.
 
 Supported Boards
 ================

arch/arm/include/rp2040/i2c_slave.h

@@ -55,7 +55,7 @@ extern "C"
  *   to the instance of struct i2c_slave_s.  This function should only be
  *   called once of a give controller.
  *
- *   Note: the same port cannot be initalized as both master and slave.
+ *   Note: the same port cannot be initialized as both master and slave.
  *
  * Input Parameters:
  *   rx_buffer     - Buffer for data transmitted to us by an I2C master.
@@ -84,7 +84,7 @@ struct i2c_slave_s *rp2040_i2c0_slave_initialize
  *   to the instance of struct i2c_slave_s.  This function should only be
  *   called once of a give controller.
  *
- *   Note: the same port cannot be initalized as both master and slave.
+ *   Note: the same port cannot be initialized as both master and slave.
  *
  * Input Parameters:
  *   rx_buffer     - Buffer for data transmitted to us by an I2C master.

arch/arm/include/rp23xx/i2c_slave.h

@@ -55,7 +55,7 @@ extern "C"
  *   to the instance of struct i2c_slave_s.  This function should only be
  *   called once of a give controller.
  *
- *   Note: the same port cannot be initalized as both master and slave.
+ *   Note: the same port cannot be initialized as both master and slave.
  *
  * Input Parameters:
  *   rx_buffer     - Buffer for data transmitted to us by an I2C master.
@@ -84,7 +84,7 @@ struct i2c_slave_s *rp23xx_i2c0_slave_initialize
  *   to the instance of struct i2c_slave_s.  This function should only be
  *   called once of a give controller.
  *
- *   Note: the same port cannot be initalized as both master and slave.
+ *   Note: the same port cannot be initialized as both master and slave.
  *
  * Input Parameters:
  *   rx_buffer     - Buffer for data transmitted to us by an I2C master.

arch/arm/src/rp23xx/Make.defs

@@ -35,14 +35,17 @@ CHIP_CSRCS += rp23xx_xosc.c
 CHIP_CSRCS += rp23xx_pll.c
 
 ifeq ($(CONFIG_SMP),y)
-CHIP_CSRCS += rp23xx_cpuindex.c
 CHIP_CSRCS += rp23xx_cpustart.c
-CHIP_CSRCS += rp23xx_cpupause.c
+CHIP_CSRCS += rp23xx_smpcall.c
 CHIP_CSRCS += rp23xx_cpuidlestack.c
 CHIP_CSRCS += rp23xx_testset.c
 CMN_ASRCS  := $(filter-out arm_testset.S,$(CMN_ASRCS))
 endif
 
+ifeq ($(CONFIG_ARCH_HAVE_MULTICPU),y)
+CHIP_CSRCS += rp23xx_cpuindex.c
+endif
+
 ifeq ($(CONFIG_RP23XX_DMAC),y)
 CHIP_CSRCS += rp23xx_dmac.c
 endif

arch/arm/src/rp23xx/hardware/rp23xx_dma.h

@@ -33,7 +33,6 @@
 
 /* Register offsets *********************************************************/
 
-
 #define RP23XX_DMA_READ_ADDR_OFFSET                  0x000000  /* DMA Read Address pointer */
 #define RP23XX_DMA_WRITE_ADDR_OFFSET                 0x000004  /* DMA Write Address pointer */
 #define RP23XX_DMA_TRANS_COUNT_OFFSET                0x000008  /* DMA Transfer Count */
@@ -240,4 +239,4 @@
 #define RP23XX_DMA_SECCFG_MISC_TIMER3_S                    (1 << 9)
 #define RP23XX_DMA_DBG_CTDREQ_MASK                         (0x3f)
 
-#endif /*__ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_DMA_H*/
+#endif /* __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_DMA_H */

arch/arm/src/rp23xx/hardware/rp23xx_pio.h

@@ -98,9 +98,9 @@
 #define RP23XX_PIO_CTRL_NEXTPREV_CLKDIV_RESTART     (1 << 26)  /* Write 1 to restart the clock dividers of state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to writing 1 to the corresponding CLKDIV_RESTART bits in those PIOs' CTRL registers */
 #define RP23XX_PIO_CTRL_NEXTPREV_SM_DISABLE         (1 << 25)  /* Write 1 to disable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to clearing the corresponding SM_ENABLE bits in those PIOs' CTRL registers */
 #define RP23XX_PIO_CTRL_NEXTPREV_SM_ENABLE          (1 << 24)  /* Write 1 to enable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to clearing the corresponding SM_ENABLE bits in those PIOs' CTRL registers. If both OTHERS_SM_ENABLE and OTHERS_SM_DISABLE are set, the disable takes precedence */
-#define RP23XX_PIO_NEXT_PIO_MASK_SHIFT              (20)    /* A mask of state machines in the neighbouring highernumbered PIO block in the system (or PIO block 0 if this is the highestnumbered PIO block) to which to apply the operations specified by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and NEXTPREV_SM_DISABLE in the same write */
+#define RP23XX_PIO_NEXT_PIO_MASK_SHIFT              (20)       /* A mask of state machines in the neighbouring highernumbered PIO block in the system (or PIO block 0 if this is the highestnumbered PIO block) to which to apply the operations specified by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and NEXTPREV_SM_DISABLE in the same write */
 #define RP23XX_PIO_NEXT_PIO_MASK_MASK               (0xf)
-#define RP23XX_PIO_PREV_PIO_MASK_SHIFT              (16)    /* A mask of state machines in the neighbouring lowernumbered PIO block in the system (or the highest-numbered PIO block if this is PIO block 0) to which to apply the operations specified by OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same write */
+#define RP23XX_PIO_PREV_PIO_MASK_SHIFT              (16)       /* A mask of state machines in the neighbouring lowernumbered PIO block in the system (or the highest-numbered PIO block if this is PIO block 0) to which to apply the operations specified by OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same write */
 #define RP23XX_PIO_PREV_PIO_MASK_MASK               (0xf)
 
 #define RP23XX_PIO_CTRL_CLKDIV_RESTART_SHIFT        (8)     /* Force clock dividers to restart their count and clear fractional accumulators. Restart multiple dividers to synchronise them. */

arch/arm/src/rp23xx/hardware/rp23xx_sha256.h

@@ -55,5 +55,4 @@
 #define RP23XX_SHA256_WDATA_MASK             (0xffffffff)
 #define RP23XX_SHA256_SUM_MASK               (0xffffffff)
 
-
 #endif /* __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_SHA256_H */

arch/arm/src/rp23xx/rp23xx_cpuindex.c

@@ -29,7 +29,7 @@
 #include "arm_internal.h"
 #include "hardware/rp23xx_sio.h"
 
-#ifdef CONFIG_SMP
+#ifdef CONFIG_ARCH_HAVE_MULTICPU
 
 /****************************************************************************
  * Public Functions