This repository contains the implementation of a RV32I RISC-V processor designed for deployment and testing on the Nexys A7 FPGA trainer kit. The project aims to build a pipelined CPU with correct hazard handling and efficient resource usage, adhering to the RV32I base integer instruction set specification.
Copyright 2024 Arwa Abdelkarim
Copyright 2024 Farida Bey
Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.