The implementation of 32-bit MIPS ISA was done using Verliog HDL. This design has 5 stage stage pipelining. The processor was synthesised on Design Compiler using NanGate 15nm library with following operating condition.
Operating Condition Name : typical
Library : NanGate_15nm_OCL
Process : Typical
Temperature : 25.00
Voltage : 0.80
Interconnect Model : balanced_tree
#See statistics.log file The schematics is very dense and shown in Schematic.pdf