Add ROC-RK3328-CC support

arch/arm/dts/Makefile

@@ -47,6 +47,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rk3288-veyron-minnie.dtb \
 	rk3328-evb.dtb \
 	rk3328-rock64.dtb \
+	rk3328-roc-cc.dtb \
 	rk3368-lion.dtb \
 	rk3368-sheep.dtb \
 	rk3368-geekbox.dtb \

arch/arm/dts/rk3328-roc-cc.dts

@@ -0,0 +1,246 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/dts-v1/;
+#include "rk3328.dtsi"
+#include "rk3328-sdram-ddr3-666.dtsi"
+
+/ {
+	model = "Firefly ROC-RK3328-CC";
+	compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
+
+	chosen {
+		stdout-path = &uart2;
+	};
+
+	vcc3v3_sdmmc: sdmmc-pwren {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3";
+		gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc5v0_otg: vcc5v0-otg-drv {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		regulator-name = "vcc5v0_otg";
+		gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc5v0_host_xhci: vcc5v0-host-xhci-drv {
+		status = "disabled";	//usb host xhci and usb otg use the same gpio to enable power
+		compatible = "regulator-fixed";
+		enable-active-high;
+		regulator-name = "vcc5v0_host_xhci";
+		gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+	};
+};
+
+&saradc {
+	status = "okay";
+};
+
+&uart2 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	card-detect-delay = <200>;
+	disable-wp;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
+	status = "okay";
+};
+
+&emmc {
+	u-boot,dm-pre-reloc;
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	supports-emmc;
+	disable-wp;
+	non-removable;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+	status = "okay";
+};
+
+&u2phy {
+        status = "okay";
+};
+
+&u2phy_otg {
+        status = "okay";
+};
+
+&u2phy_host {
+        status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb20_otg {
+	vbus-supply = <&vcc5v0_otg>;
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	//vbus-supply = <&vcc5v0_host_xhci>;
+	vbus-supply = <&vcc5v0_otg>;
+	status = "okay";
+	maximum-speed = "high-speed";
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <168>;
+	i2c-scl-falling-time-ns = <4>;
+	status = "okay";
+
+	rk805: pmic@18 {
+		compatible = "rockchip,rk805";
+		status = "okay";
+		reg = <0x18>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+		gpio-controller;
+		#gpio-cells = <2>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk805-clkout2";
+
+		pwrkey {
+			status = "okay";
+		};
+
+		led1 {
+			label = "standby";
+		};
+
+		led2 {
+			label = "power";
+		};
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-min-microvolt = <712500>;
+				regulator-max-microvolt = <1450000>;
+				regulator-ramp-delay = <6001>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+
+			vdd_arm: DCDC_REG2 {
+				regulator-name = "vdd_arm";
+				regulator-min-microvolt = <712500>;
+				regulator-max-microvolt = <1450000>;
+				regulator-ramp-delay = <6001>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_io: DCDC_REG4 {
+				regulator-name = "vcc_io";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vdd_18: LDO_REG1 {
+				regulator-name = "vdd_18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_18emmc: LDO_REG2 {
+				regulator-name = "vcc_18emmc";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_10: LDO_REG3 {
+				regulator-name = "vdd_10";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+		};
+	};
+};
+
+&pinctrl {
+	pmic {
+		pmic_int_l: pmic-int-l {
+		rockchip,pins =
+			<1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;	/* gpio1_d0 */
+		};
+	};
+};
+

arch/arm/mach-rockchip/rk3328/Kconfig

@@ -22,6 +22,17 @@ config TARGET_ROCK64_RK3328
 	  USB 3.0 and many others peripheral devices interface for makers
 	  to integrate with sensors and devices
 
+config TARGET_ROC_RK3328_CC
+        bool "ROC-RK3328-CC board, "
+        select BOARD_LATE_INIT
+        help
+          ROC-RK3328-CC is a Raspberry Pi-2 sized 4K60P HDR Media Board Computer
+          powered by Rockchip RK3328 Quad-Core ARM Cortex A53 64-Bit Processor
+          and support up to 4GB 2133MHz DDR4 memory.
+          It provides eMMC module socket, MicroSD Card slot, Pi-2 Bus, Pi-P5+ Bus,
+          USB 3.0 and many others peripheral devices interface for makers
+          to integrate with sensors and devices
+
 endchoice
 
 config SYS_SOC
@@ -32,5 +43,6 @@ config SYS_MALLOC_F_LEN
 
 source "board/rockchip/evb_rk3328/Kconfig"
 source "board/rockchip/rock64_rk3328/Kconfig"
+source "board/rockchip/roc_rk3328_cc/Kconfig"
 
 endif

arch/arm/mach-rockchip/sdram_common.c

@@ -14,7 +14,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 size_t rockchip_sdram_size(phys_addr_t reg)
 {
-	u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
+        u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4, dbw, bg;
 	size_t chipsize_mb = 0;
 	size_t size_mb = 0;
 	u32 ch;
@@ -37,16 +37,20 @@ size_t rockchip_sdram_size(phys_addr_t reg)
 			SYS_REG_BW_MASK));
 		row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
 			SYS_REG_ROW_3_4_MASK;
+     		dbw = sys_reg >> SYS_REG_DBW_SHIFT(ch) & SYS_REG_DBW_MASK;
+                /* only used by DDR4 */
+                bg = (dbw == 1) ? 1 : 2;
 
-		chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
+                chipsize_mb = (1 << (cs0_row + col + bg + bk + bw - 20));
 
 		if (rank > 1)
 			chipsize_mb += chipsize_mb >> (cs0_row - cs1_row);
 		if (row_3_4)
 			chipsize_mb = chipsize_mb * 3 / 4;
 		size_mb += chipsize_mb;
-		debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d\n",
-		      rank, col, bk, cs0_row, bw, row_3_4);
+                debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d dbw %d\n",
+                     rank, col, bk, cs0_row, bw, row_3_4, dbw);
+
 	}
 
 	return (size_t)size_mb << 20;

board/rockchip/roc_rk3328_cc/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_ROC_RK3328_CC
+
+config SYS_BOARD
+	default "roc_rk3328_cc"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "roc_rk3328_cc"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif

board/rockchip/roc_rk3328_cc/Makefile

@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2018 FIREFLY
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= roc-rk3328-cc.o

board/rockchip/roc_rk3328_cc/roc-rk3328-cc.c

@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2018 FIREFLY
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dwc3-uboot.h>
+#include <power/regulator.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+