Fix before merge

kernel/cpu/riscv/include/cpu/interrupt.h

@@ -4,6 +4,7 @@
 #pragma once
 
 #include "cpu/regs.h"
+#include "cpu/riscv.h"
 
 #include <stdbool.h>
 

kernel/cpu/riscv/include/cpu/isr_ctx.h

@@ -4,6 +4,7 @@
 #pragma once
 
 #include "cpu/regs.h"
+#include "cpu/riscv.h"
 
 #ifndef __ASSEMBLER__
 #include "cpulocal.h"

kernel/cpu/riscv/include/cpu/mmu.h

@@ -3,8 +3,8 @@
 
 #pragma once
 
+#include "cpu/riscv.h"
 #include "memprotect.h"
-#include "riscv.h"
 
 #include <stdbool.h>
 #include <stddef.h>

kernel/cpu/riscv/include/cpu/riscv.h

@@ -3,6 +3,20 @@
 
 #pragma once
 
+// Undef x86 macros because intellisense doesn't recognise RISC-V.
+#ifndef __riscv_xlen
+#ifdef __x86_64__
+#define __riscv_xlen 64
+#else
+#define __riscv_xlen 32
+#endif
+#endif
+#undef __x86_64__
+#undef __i386__
+#ifndef __riscv
+#define __riscv
+#endif
+
 
 
 /* ==== RISC-V MSTATUS DEFINITION ==== */

kernel/cpu/riscv/include/cpu/riscv_pmp.h

@@ -7,6 +7,7 @@
 
 #include "assertions.h"
 #include "attributes.h"
+#include "cpu/riscv.h"
 #include "meta.h"
 #include "port/hardware.h"
 #include "port/hardware_allocation.h"

kernel/cpu/riscv/include/cpu/riscv_sbi.h

@@ -3,6 +3,8 @@
 
 #pragma once
 
+#include "cpu/riscv.h"
+
 
 
 // Completed successfully.

kernel/cpu/riscv/src/sbi_time.c

@@ -25,10 +25,16 @@ static uint64_t base_tick;
 // Get the current time in ticks.
 static inline uint64_t time_ticks() {
 #if __riscv_xlen == 32
-    uint32_t ticks_lo;
-    uint32_t ticks_hi;
-    asm("rdtime %0; rdtimeh %1" : "=r"(ticks_lo), "=r"(ticks_hi));
-    uint64_t ticks = ((uint64_t)ticks_hi << 32) | ticks_lo;
+    uint32_t ticks_lo0, ticks_lo1;
+    uint32_t ticks_hi0, ticks_hi1;
+    asm("rdtimeh %0; rdtime %1" : "=r"(ticks_hi0), "=r"(ticks_lo0));
+    asm("rdtimeh %0; rdtime %1" : "=r"(ticks_hi1), "=r"(ticks_lo1));
+    uint64_t ticks;
+    if (ticks_hi0 != ticks_hi1) {
+        ticks = ((uint64_t)ticks_hi1 << 32) | ticks_lo1;
+    } else {
+        ticks = ((uint64_t)ticks_hi0 << 32) | ticks_lo0;
+    }
 #else
     uint64_t ticks;
     asm("rdtime %0" : "=r"(ticks));

kernel/cpu/riscv/src/smp.c

@@ -113,6 +113,7 @@ void smp_init_dtb(dtb_handle_t *dtb) {
     uint32_t cpu_acells = dtb_read_uint(dtb, cpus, "#address-cells");
     assert_always(cpu_acells && cpu_acells <= sizeof(size_t) / 4);
     assert_always(dtb_read_uint(dtb, cpus, "#size-cells") == 0);
+    size_t bsp_hartid = smp_req.response->bsp_hartid;
 
     while (cpu) {
         // Detect usable architecture.
@@ -139,33 +140,50 @@ void smp_init_dtb(dtb_handle_t *dtb) {
         dtb_prop_t *reg = dtb_get_prop(dtb, cpu, "reg");
         assert_always(reg && reg->content_len == 4 * cpu_acells);
         size_t cpuid = dtb_prop_read_uint(dtb, reg);
-        logkf(LOG_INFO, "Detected CPU #%{d} ID %{size;d}", cpu_index, cpuid);
+        int    detected_cpu;
+        if (cpuid == bsp_hartid) {
+            detected_cpu = 0;
+        } else {
+            detected_cpu = smp_count;
+            smp_count++;
+        }
+        logkf(LOG_INFO, "Detected CPU #%{d} ID %{size;d}", detected_cpu, cpuid);
 
         // Add to the maps.
         smp_map_t new_ent = {
-            .cpu   = cpu_index++,
+            .cpu   = detected_cpu,
             .cpuid = cpuid,
         };
         assert_always(array_len_sorted_insert(&smp_map, sizeof(smp_map_t), &smp_map_len, &new_ent, smp_cpuid_cmp));
         assert_always(array_len_sorted_insert(&smp_unmap, sizeof(smp_map_t), &smp_unmap_len, &new_ent, smp_cpu_cmp));
 
         cpu = cpu->next;
     }
+    int cur_cpu = smp_cur_cpu();
 
+    // Allocate status per CPU.
     cpu_status = calloc(smp_count, sizeof(smp_status_t));
     assert_always(cpu_status);
-    cpu_status[smp_cur_cpu()] = (smp_status_t){
+    cpu_status[cur_cpu] = (smp_status_t){
         .did_jump = true,
         .is_up    = true,
     };
+
+    // Transfer booting CPU's CPU-local data to this array.
+    bool ie = irq_disable();
+
+    cpu_status[cur_cpu].cpulocal = *isr_ctx_get()->cpulocal;
+    isr_ctx_get()->cpulocal      = &cpu_status[cur_cpu].cpulocal;
+
+    irq_enable_if(ie);
 }
 
 // The the SMP CPU index of the calling CPU.
 int smp_cur_cpu() {
     if (!smp_map_len) {
         return 0;
     }
-    return smp_get_cpu(isr_ctx_get()->cpulocal->cpuid);
+    return isr_ctx_get()->cpulocal->cpu;
 }
 
 // Get the SMP CPU index from the CPU ID value.
@@ -206,9 +224,15 @@ static NAKED void cpu1_init0_limine(struct limine_smp_info *info) {
 
 // Second stage entrypoint for secondary CPUs.
 static void cpu1_init1_limine(struct limine_smp_info *info) {
-    isr_ctx_t tmp_ctx = {0};
-    tmp_ctx.flags     = ISR_CTX_FLAG_KERNEL;
-    __builtin_unreachable();
+    int       cur_cpu       = (int)info->extra_argument;
+    isr_ctx_t tmp_ctx       = {0};
+    tmp_ctx.flags           = ISR_CTX_FLAG_KERNEL;
+    tmp_ctx.cpulocal        = &cpu_status[cur_cpu].cpulocal;
+    tmp_ctx.cpulocal->cpuid = info->hartid;
+    tmp_ctx.cpulocal->cpu   = cur_cpu;
+    asm("csrw sscratch, %0" ::"r"(&tmp_ctx));
+    cpu_status[cur_cpu].entrypoint();
+    __builtin_trap();
 }
 
 // Power on another CPU.
@@ -224,7 +248,7 @@ bool smp_poweron(int cpu, void *entrypoint, void *stack) {
     // Start the CPU up.
     if (!cpu_status[cpu].did_jump) {
         for (uint64_t i = 0; i < smp_req.response->cpu_count; i++) {
-            if (smp_req.response->cpus[i]->processor_id == smp_map[cpu].cpuid) {
+            if (smp_req.response->cpus[i]->hartid == smp_map[cpu].cpuid) {
                 smp_req.response->cpus[i]->extra_argument = cpu;
                 atomic_store(&smp_req.response->cpus[i]->goto_address, &cpu1_init0_limine);
                 cpu_status[cpu].did_jump = true;

kernel/include/cpulocal.h

@@ -14,6 +14,8 @@
 typedef struct {
     // Current CPU ID.
     size_t            cpuid;
+    // Current SMP CPU inder.
+    int               cpu;
     // ISR stack top.
     size_t            isr_stack_top;
     // ISR stack bottom.

kernel/port/esp32c6/include/port/port.h

@@ -9,6 +9,8 @@
 
 // Early hardware initialization.
 void port_early_init();
+// Post-heap hardware initialization.
+void port_postheap_init();
 // Full hardware initialization.
 void port_init();
 // Power off.

kernel/port/esp32c6/src/memprotect.c

@@ -81,6 +81,10 @@ void memprotect_early_init() {
     );
 }
 
+// Initialise memory protection driver.
+void memprotect_postheap_init() {
+}
+
 // Initialise memory protection driver.
 void memprotect_init() {
 }

kernel/port/esp32c6/src/port.c

@@ -48,6 +48,10 @@ void port_early_init() {
     PCR.uart0_conf.uart0_clk_en          = true;
 }
 
+// Post-heap hardware initialization.
+void port_postheap_init() {
+}
+
 // Full hardware initialization.
 void port_init() {
     extern void esp_i2c_isr();

kernel/port/esp32p4/include/port/port.h

@@ -9,6 +9,8 @@
 
 // Early hardware initialization.
 void port_early_init();
+// Post-heap hardware initialization.
+void port_postheap_init();
 // Full hardware initialization.
 void port_init();
 // Power off.

kernel/port/esp32p4/src/interrupt.c

@@ -162,7 +162,7 @@ void riscv_interrupt_handler() {
 
     intmtx_t *intmtx = intmtx_local();
 
-    for (size_t i = 0; i < IRQ_GROUPS; i++) {
+    for (int i = 0; i < IRQ_GROUPS; i++) {
         uint32_t pending = intmtx->pending[i] & atomic_load(&enable_mask[i]);
         while (pending) {
             int      lsb_pos   = __builtin_ctz(pending);

kernel/port/esp32p4/src/memprotect.c

@@ -81,6 +81,10 @@ void memprotect_early_init() {
     );
 }
 
+// Initialise memory protection driver.
+void memprotect_postheap_init() {
+}
+
 // Initialise memory protection driver.
 void memprotect_init() {
 }

kernel/port/esp32p4/src/port.c

@@ -28,25 +28,6 @@ cpulocal_t port_cpu1_local = {.cpuid = 1};
 
 
 
-void lolfunc() {
-    asm(".option push;"
-        ".option norelax;"
-        "la gp, __global_pointer$;"
-        ".option pop;");
-    logk_from_isr(LOG_INFO, "This be CPU1");
-    while (1) asm("wfi");
-}
-
-// Start CPU1.
-void port_start_cpu1() {
-    cpu_utility_ll_stall_cpu(1);
-    HP_SYS_CLKRST.soc_clk_ctrl0.reg_core1_cpu_clk_en = true;
-    HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_core1_global = false;
-    cpu_utility_ll_reset_cpu(1);
-    ets_set_appcpu_boot_addr((uint32_t)&lolfunc);
-    cpu_utility_ll_unstall_cpu(1);
-}
-
 // Early hardware initialization.
 void port_early_init() {
     // Set CPU-local data pointer.
@@ -55,10 +36,12 @@ void port_early_init() {
     pmu_init();
 }
 
+// Post-heap hardware initialization.
+void port_postheap_init() {
+}
+
 // Full hardware initialization.
 void port_init() {
-    // port_start_cpu1();
-    // while (1) asm("wfi");
     extern void esp_i2c_isr();
     irq_ch_set_isr(ETS_I2C0_INTR_SOURCE, esp_i2c_isr);
     irq_ch_enable(ETS_I2C0_INTR_SOURCE);

kernel/port/esp_common/include/port/time.h

@@ -0,0 +1,7 @@
+
+// SPDX-License-Identifier: MIT
+
+#pragma once
+
+// Initialise timer and watchdog subsystem.
+void time_init_dtb();

kernel/port/esp_common/src/hwtimer.c

@@ -20,6 +20,7 @@
 #include <soc/clk_tree_defs.h>
 #include <soc/lp_wdt_struct.h>
 #include <soc/soc.h>
+#include <soc/soc_caps.h>
 #include <soc/timer_group_struct.h>
 
 #ifdef CONFIG_TARGET_esp32c6
@@ -105,6 +106,7 @@ void timer_set_freq(int timerno, frequency_hz_t freq) {
         case 1: clksrc = HP_SYS_CLKRST.peri_clk_ctrl20.reg_timergrp0_t1_src_sel; break;
         case 2: clksrc = HP_SYS_CLKRST.peri_clk_ctrl21.reg_timergrp1_t0_src_sel; break;
         case 3: clksrc = HP_SYS_CLKRST.peri_clk_ctrl21.reg_timergrp1_t1_src_sel; break;
+        default: __builtin_unreachable();
     }
 #endif
 #ifdef CONFIG_TARGET_esp32c6