cleanup pl230 test

betrusted-io · Jan 20, 2024 · d4e6cbc · d4e6cbc
1 parent d990a4d
commit d4e6cbc
Show file tree

Hide file tree

Showing 2 changed files with 32 additions and 18 deletions.
diff --git a/libs/xous-pl230/Cargo.toml b/libs/xous-pl230/Cargo.toml
@@ -12,6 +12,9 @@ bitfield = "0.13.2"
 xous-pio = { path = "../xous-pio", optional = true, default-features = false }
 pio-proc = "0.2.2"
 pio = "0.2.1"
+cramium-hal = { path = "../cramium-hal", optional = true, features = [
+    "baremetal",
+] }
 
 [target.'cfg(target_os = "xous")'.dependencies]
 xous = "0.9.57"
@@ -26,5 +29,5 @@ pio = ["xous-pio"]
 dma-mainram = []
 baremetal = []
 
-tests = ["pio"]
+tests = ["pio", "cramium-hal"]
 default = ["tests", "pio"]
diff --git a/libs/xous-pl230/src/pl230_tests/units.rs b/libs/xous-pl230/src/pl230_tests/units.rs
@@ -12,9 +12,9 @@ pub fn lfsr_next(state: u32) -> u32 {
 
 pub fn basic_tests(pl230: &mut Pl230) -> bool {
     report_api("channels", pl230.csr.rf(utra::pl230::STATUS_CHNLS_MINUS1) + 1);
-    //report_api("id0", pl230.csr.r(utra::pl230::PERIPH_ID_0));
-    //report_api("id1", pl230.csr.r(utra::pl230::PERIPH_ID_1));
-    //report_api("id2", pl230.csr.r(utra::pl230::PERIPH_ID_2));
+    report_api("id0", pl230.csr.r(utra::pl230::PERIPH_ID_0));
+    report_api("id1", pl230.csr.r(utra::pl230::PERIPH_ID_1));
+    report_api("id2", pl230.csr.r(utra::pl230::PERIPH_ID_2));
 
     // conjure the DMA control structure in IFRAM0. In order to guarantee Rust
     // semantics, it must be initialized to 0: 4 word-sized entries * 8 channels * 2 banks = 4 * 8 * 2
@@ -27,9 +27,9 @@ pub fn basic_tests(pl230: &mut Pl230) -> bool {
         unsafe { (utralib::HW_IFRAM0_MEM as *mut ControlChannels).as_mut().unwrap() };
 
     // read the status register
-    // report_api("status", pl230.csr.r(utra::pl230::STATUS));
+    report_api("status", pl230.csr.r(utra::pl230::STATUS));
     pl230.csr.wfo(utra::pl230::CFG_MASTER_ENABLE, 1); // enable
-    // report_api("status after enable", pl230.csr.r(utra::pl230::STATUS));
+    report_api("status after enable", pl230.csr.r(utra::pl230::STATUS));
 
     const DMA_LEN: usize = 16;
     // setup the PL230 to do a simple transfer between two memory regions
@@ -128,16 +128,17 @@ pub fn basic_tests(pl230: &mut Pl230) -> bool {
 
 #[cfg(feature = "pio")]
 pub fn pio_test(pl230: &mut Pl230) -> bool {
+    use cramium_hal::iox;
     use xous_pio::*;
 
-    let iox_csr = utra::iox::HW_IOX_BASE as *mut u32;
-    unsafe {
-        iox_csr.add(0x8 / core::mem::size_of::<u32>()).write_volatile(0b0101_0101_0101_0101); // PBL
-        iox_csr.add(0xC / core::mem::size_of::<u32>()).write_volatile(0b0101_0101_0101_0101); // PBH
-        iox_csr.add(0x10 / core::mem::size_of::<u32>()).write_volatile(0b0101_0101_0101_0101); // PCL
-        iox_csr.add(0x14 / core::mem::size_of::<u32>()).write_volatile(0b0101_0101_0101_0101); // PCH
-        iox_csr.add(0x200 / core::mem::size_of::<u32>()).write_volatile(0xffffffff); // PIO sel port D31-0
-    }
+    report_api("channels", pl230.csr.rf(utra::pl230::STATUS_CHNLS_MINUS1) + 1);
+    report_api("id0", pl230.csr.r(utra::pl230::PERIPH_ID_0));
+    report_api("id1", pl230.csr.r(utra::pl230::PERIPH_ID_1));
+    report_api("id2", pl230.csr.r(utra::pl230::PERIPH_ID_2));
+
+    let mut iox = iox::Iox::new(utralib::generated::HW_IOX_BASE as *mut u32);
+    let pin = iox.set_pio_bit_from_port_and_pin(iox::IoxPort::PB, 15).unwrap();
+    report_api("Configured PIO pin: ", pin as u32);
 
     // setup PIO block as DMA target -- just take the data coming into the TX
     // FIFO and send it to the GPIO pins.
@@ -153,10 +154,9 @@ pub fn pio_test(pl230: &mut Pl230) -> bool {
     sm_a.sm_set_enabled(false);
     a_prog.setup_default_config(&mut sm_a);
     sm_a.config_set_out_pins(0, 32);
-    sm_a.sm_set_pindirs_with_mask(0xFFFF_FFFF, 0xFFFF_FFFF);
     sm_a.config_set_clkdiv(133.0); // have it run slow so this test operates in the background
     sm_a.config_set_out_shift(false, true, 32);
-    sm_a.sm_set_pindirs_with_mask(0x10, 0x10);
+    sm_a.sm_set_pindirs_with_mask(1 << pin as usize, 1 << pin as usize);
     sm_a.sm_init(a_prog.entry());
     sm_a.sm_clear_fifos(); // ensure the fifos are cleared for this test
 
@@ -185,14 +185,17 @@ pub fn pio_test(pl230: &mut Pl230) -> bool {
     // safety: we guarantee that the pointer is aligned and initialized
     let cc_struct: &mut ControlChannels =
         unsafe { (utralib::HW_IFRAM0_MEM as *mut ControlChannels).as_mut().unwrap() };
+    report_api("status", pl230.csr.r(utra::pl230::STATUS));
     pl230.csr.wfo(utra::pl230::CFG_MASTER_ENABLE, 1); // enable
+    report_api("status after enable", pl230.csr.r(utra::pl230::STATUS));
 
     const DMA_LEN: usize = 1024;
-    let mut region_a = [0u32; DMA_LEN];
+    // DMA can't happen from main RAM, only IFRAM.
+    let region_a = unsafe { core::slice::from_raw_parts_mut(utralib::HW_IFRAM0_MEM as *mut u32, DMA_LEN) };
     let mut state = 0x1111_0000;
     for d in region_a.iter_mut() {
         *d = state;
-        state += 0x0101_0101;
+        state = crate::pl230_tests::units::lfsr_next(state);
     }
 
     cc_struct.channels[0].dst_end_ptr =
@@ -234,6 +237,14 @@ pub fn pio_test(pl230: &mut Pl230) -> bool {
     // now enable the PIO block so that DMA reqs can run
     sm_a.sm_irq0_source_enabled(PioIntSource::TxNotFull, true);
     sm_a.sm_set_enabled(true);
+
+    let mut timeout = 0;
+    while (DmaChanControl(cc_struct.channels[0].control).cycle_ctrl() != 0) && timeout < 32 {
+        // report_api("dma progress ", cc_struct.channels[0].control);
+        report_api("progress as baseptr[2]", unsafe { cc_struct.channels.as_ptr().read() }.control);
+        timeout += 1;
+    }
+
     report_api("pio irq", if sm_a.sm_irq0_status(None) { 1 } else { 0 });
 
     // irq0 will now fire and cause the DMA data to clock into the PIO block until the length is exhausted.